Timing Violation Error using a NI FPGA FlexRIO CLIP - Requirement 0,00ns Missed

Updated Jul 7, 2020

Reported In


  • PXI FPGA Module for FlexRIO


  • LabVIEW FPGA Module

Issue Details

In NI FlexRIO there are several CLIP directly usable like the SerDes Connector CLIP Reference.
Why do I get a Timing Violation Error using the CLIP nodes to access the Data?
The Timing Violation Error states a missed Requirement of 0,00ns by some ns.


For a CLIP node you must not use the different CLIP Properties mixed with Non-CLIP Properties in the same Node, nor the same SCTL.