Used Primarily to synchronize two modules with different sampling rates. For examples, when synchronization between analog modules and digital modules is required, the analog module can configure the edge of the digital signal to wait if it cannot be read from a single FPGA I/O node. This example is below.
This is an example that does the following: When rising edge of digital signal generated in channel0 of Mod1, 1V is output in Channel0 of Mod3, and when falling edge, 0V is output.
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