Solution
You can generate simple digital pulse using While loop, Timing configuration and FPGA I/O node. The type of input terminal of FPGA I/O node should be single value in LabVIEW FPGA. So, The boolean value(True/False) should be aligned with the proper timing of the intended digital pulse train's frequency.
For example, This below figure shows cRIO with digital cModule (ex. NI 9401) FPGA generation of digital pulse train. It's frequency is 500kHz. While loop's iteration time is determined by Loop timer within 2 uSec. And between high and low logic, time span is determined by wait within 1 uSec.
This knowledge base is not the only way could make digital pusle train. Depending on your application, you can use various different ways.