Solution
In the NI 9775 Continuous mode example, the FPGA code does not have a timing configuration function in the while loop. Nevertheless, the data rates set by the FPGA I/O Property repeats the loop. The reason is that the FPGA I/O node resource is compiled to the most time-consuming component in the loop. So, the loop rates are dependent automatically.
For example, If the Continuous data rate is set to 1MS/s, loop is repeated with 1 us and the loop maintains the 1MS/s speed within the loop to the extent that the sum of all function time included is not more than 1 us. But if not, it’ll lose the intended speed. It could be recognized after compilation only. Refer to below figure. After compilation of FPGA code included with Tick Count, which indicates 40 ticks.
In continuous mode, the NI 9775 transfers real-time data to the chassis at an aggregate rate of 4MS/s across all channels. You can configure the data rate through the module property Continuous Data Rate like below. And, the maximum speed rate is limited in 1MS/s.
This is because the maximum speed of 4MS/sis being shared amongst all 4 channels, thus limiting the sample rate of 1 MS/s per channel. To achieve the continuous sample rate of 4 MS/s for one channel, you can disable the other 3 channels in the NI 9775 Module Properties window:
- In the Project Explorer, expand RT CompactRIO Target>>Chassis>>FPGA Target and then locate the NI 9775 module item with the blue C Series module icon
. - Right-click on the 9775 module item and select Properties.
- In the Channel Configuration box, select 3 of the 4 channels and uncheck the Enable box. This will allow you to achieve a continuous data rate of 4 MS/s for the remaining enabled channel. You will need to recreate the constant or control wired into the Continuous Data Rate property.