NI 9775 FPGA Timing Configuration in Continuous Mode

Updated Nov 3, 2020

Reported In


  • NI-9775


  • LabVIEW FPGA Module
  • LabVIEW
  • LabVIEW Real-Time Module

Issue Details

  • In NI FPGA example code 'NI 9775 Getting Started Continuous mode(FPGA)', why there is no any timing configuration on the loop?
  • In NI 9775 help document, 4MS/s seems maximum data rate for communication between I/O node and chassis. But, in an example of this module, continuous Data Rate in FPGA I/O Property input was limited in speed 1.000MS/s. Why?


In the NI 9775 Continuous mode example, the FPGA code does not have a timing configuration function in the while loop. Nevertheless, the data rates set by the FPGA I/O Property repeats the loop. The reason is that the FPGA I/O node resource is compiled to the most time-consuming component in the loop. So, the loop rates are dependent automatically.

For example, If the Continuous data rate is set to 1MS/s, loop is repeated with 1 us and the loop maintains the 1MS/s speed within the loop to the extent that the sum of all function time included is not more than 1 us. But if not, it’ll lose the intended speed. It could be recognized after compilation only. Refer to below figure. After compilation of FPGA code included with Tick Count, which indicates 40 ticks. 

In continous mode, the NI 9775 transfers real-time data to the chassis at an aggregate rate of 4MS/s across all channels. You can configure the data rate through the module property Continous Data Rate like below. And, the maximum speed rate is limited in 1MS/s. 
Because, The maximum speed of 4MS/s refers to the rate at which data is transferred from I/O to Chassis, thus limiting the sample rate of 1MS/s per channel based on 4 channel. The sample rate of 1 MS/s is the same for 1 channel as 4 channels when programming in FPGA, to achieve the continuous sample rate of 4 MS/s for one channel requires programming in NI-DAQmx.  

Additional Information

If you wanted to check the loop time of FPGA loop, refer this page.