Checking if a PXI Chassis Is Locked to an External 10 MHz Clock Input

Updated Jan 16, 2023

Environment

Hardware

  • PXI Chassis

This article explains how to check programmatically if a PXI is locked to the clock signal connected to the 10MHz REF IN connector.

First, it is essential to understand that this process is done automatically by the hardware:
  • The PXI chassis detects and prioritizes an external clock signal connected to the 10 MHz REF IN connector and phase-locks the PXI clocks to it for synchronization purposes. This is explained in more detail in the manual of your chassis, for example here you can find it for the PXIe-1092: 10 MHz Input Reference.
  • This facilitates the programming and allows the user to phase-lock to an external clock without additional effort. 
However, there are applications where users need to double-check if the external clock has been appropriately connected to the Ref In connector, if someone disconnected it from the clock source, or if the external clock is ready to be used, and some other unexpected situations that can happen outside the PXI chassis that can lead to different issues with their application if they don't double-check this. For this particular case, this process can be followed. 

As of PXI Platform Service 18.0, these attributes are now accessible in LabVIEW.  

1. Open the functions palette in LabVIEW (right-click in the Block Diagram window) >> Measurement IO >> NI System Configuration >> Hardware >> Hardware Node. 
2. After placing the hardware in the block diagram, click on the default property selected (below System Hardware) and look for Devices & Chassis >> Bus Specific >> PXI CLK10 Source.

process.jfif
3. This property will display an enum that will show which is the source of your PXI clock.
enum.jfif