Error: Power Optimization When Compiling FPGA VI Locally in LabVIEW

Issue Details

I am trying to compile a simple example FPGA VI using the local compile server, and the following error is generated in the error log:

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
ERROR: [Vivado_Tcl 4-131] Power Optimization encountered an exception: ERROR: [Common 17-70] Application Exception: Power Optimization aborted at r:/builds/2019.1.1/continuous/2019_06_20_2573335/src/shared/pwropt/core/cmd_parser.cpp:551
ERROR: [Vivado_Tcl 4-130] Power Optimization encountered an error.
Ending Power Optimization Task | Checksum: c3ff3092

Solution

To solve this problem disable BRAM power optimization in compilation properties:
You can access the Compilation properties by doing the following:

Right-click on an FPGA VI, and Create Build Specification (1), and/or edit an existing one under Build Specifications (2):

Right-click on a Build Specification and choose: Properties


Under the Category tab select Xilinx options and choose Custom from the Implementation strategy options.

In the Design optimization directive menu choose Disable BRAM power optimization

After performing the steps above, starting the compilation again will solve the issue.