Deploying Halfwave Rectifier Simscape Model in FPGA Using NI VeriStand

This article focuses on deploying a high-fidelity Halfwave Rectifier Simulation Model (containing Simscape™ blocks) in FPGA using NI VeriStand. The workflow in the article is divided into three categories for deploying the Half Wave Rectifier Model directly on FPGA at the target rate of 40MHz for a closed-loop simulation system.

1. Compile the Half Wave Rectifier Simscape Model to Simulink HDL Implementation Model - Using Simscape HDL Workflow Advisor.
2. Convert Simulink HDL Implementation Model into NI FPGA Bit Files - Using the HDL Coder Support Package for NI FPGA Hardware Add-On for generating bit files for NI FPGA hardware from HDL Coder by providing LabVIEW FPGA integration.
3. Deploying the Generated Half Wave Rectifier bit file on FPGA Real-Time Target Using NI VeriStand- Using FPGA Add-On Custom Device

 
The outcome of this article is to demonstrate the enhanced workflow of deploying Simscape models on NI FPGA to be tested in real-time targets using NI VeriStand. The intended audiences are users who work closely with Model-In-Loop & Hardware-In-Loop Validation Testing.

Pre Requisite Knowledge Required:

1. Matlab Simulink® Modeling
2. NI VeriStand 2021 R2
3. FPGA Addon Custom Device
4. IP to FPGA Conversion Utility

Compile the Half Wave Rectifier Simscape Model to Simulink HDL Implementation Model

1. Open Generate HDL Code for Simscape Models example which shows how to generate HDL code for a halfwave rectifier model that uses Simscape™ blocks using Simscape HDL Workflow Advisor.

2. Follow the steps as mentioned in the example document till the Open and Examine HDL Implementation Model section.
3. Note, the Advisor generates an HDL implementation model and state-space validation models are saved in C:\Users\XX\Documents\Half Wave Rectifier Example\sschdl\HalfWaveRectifier_HDL.
   1. The implementation model has the same name as the original Simscape model and uses the prefix gmStateSpaceHDL_.
   2. The state-space validation model has the same name as the implementation model and uses the postfix _vnl.

Convert Simulink HDL Implementation Model into NI FPGA Bit Files

1. Refer to Generating NI FPGA Bitfile from The MathWorks®, Inc.Simulink®, HDL Coder™ & follow the steps mentioned in Generate NI FPGA Bitfile section using HDL Workflow Advisor.
2. Once the compilation is successful, the generated bit file should be located at this file path: C:\Users\XXX\Documents\Half Wave Rectifier Example\hdl_prj\LabVIEW\FPGA Bitfiles\HDL_Subsystem.lvbitx.

Deploying the Generated Half Wave Rectifier Bit File on FPGA Real-Time Target Using NI VeriStand

1. Open NI VeriStand 2021 R2 and create a new project.
2. Open the System Explorer & configure the System Definition File to connect to PXI Linux RT OS.
3. Add the FPGA Add On Custom Device to the current project.
4. Navigate to the FPGA Settings>> Bitfile path to load the bit file. Make sure the RIO Device name matches the FPGA device name present in NI MAX.
5. Add the required Inputs & Outputs by selecting the Available Registers & click Add Selected.
6. Add a Sine Wave Model by clicking Simulation Model>> Models.
7. Save the System Definition File.
8. Open the Mapping Diagram & connect the outport of the Sine Wave Model to the Half Wave Rectifier Model's Inport Vin.

9. Deploy the VeriStand Project.

After following the steps mentioned in the article, the user is able to run the Half Wave Rectifier Simscape Model in FPGA using NI VeriStand. The results in the VeriStand Screen are similar to the simulation results thus verifying the model logic is working as expected in real-time sceanrio.