Generating NI FPGA Bitfile from The MathWorks®, Inc.Simulink®, HDL Coder™

Updated Nov 8, 2022



  • PXIe-7868
  • PXIe-7867


  • Simulink
  • LabVIEW
  • LabVIEW FPGA Module
  • IP to FPGA Conversion Utility

Operating System

  • Windows
  • LabVIEW Real-Time (NI Linux Real-Time)


  • HDL Coder™
  • HDL Coder™ Support Package for NI FPGA Hardware
  • NI R Series Multifunction RIO with LabVIEW Support (32-bit)

This article will explain and walk through how to use the HDL Coder™ Support Package for NI FPGA Hardware to generate NI FPGA bitfile from the MathWorks®, Inc. Simulink®, HDL Coder™. This toolbox enables users to remain within Simulink and the HDL Coder Workflow Advisor to generate a bitfile from a Simulink model. The first release specifically supports the NI PXIe-7867 and NI PXIe-7868. Users can now take HDL Coder compatible models and directly compile a bitfile while remaining within Simulink, including the ability to map model port I/O to board I/O and registers. 

An earlier approach used a manual process that required LabVIEW expertise. Now the whole generation process can be done within the Simulink® environment without any LabVIEW FPGA experience.

Setting Up the Software Environment

Please refer to the Github page for software version compatibility and install the software in the following order,

1.    Install the supported versions of MathWorks MATLAB®, Simulink®, and HDL Coder™.
2.    Install and activate LabVIEW Full or Professional Development Systems (32-bit), LabVIEW FPGA Module (32-bit), NI R Series Multifunction RIO LabVIEW Support (32-bit), and IP to FPGA Conversion Utility.
3.    Install HDL Coder™ Support Package for NI FPGA Hardware from MATLAB® Add-Ons Explorer or download and install from Github.

Generate NI FPGA Bitfile

1.    Before generating bitfile, Simulink HDL model file must be completed and verified in HDL Coder™.
2.    Open the MATLAB® Help Documentation for HDL Coder™ Support Package for NI FPGA Hardware. 
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3.    Follow the help contents in Getting Started with HDL Coder™ Support Package for NI FPGA Hardware to set MATLAB® compiler, select hardware target, set FPGA I/O Interface and model frequency, check model settings, configure HDL code generation and generate NI FPGA hardware bitfiles.

4.    When bitfile is generated successfully, you can see the status from HDL Workflow Advisor and compilation window. 
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Next Steps

You can use the bitfile in NI LabVIEW or NI VeriStand.

1.    NI LabVIEW
The bitfile can be called in LabVIEW as any other NI FPGA bitfiles. More materials about the LabVIEW FPGA module can be found in NI.

2.    NI VeriStand
FPGA Addon custom device is needed. This module is installed by default for VeriStand 2020 R5 and above version. Quick Start Guide can be accessed in Github or local disk: %Public%\Documents\National Instruments\NI VeriStand (Year)\Custom Devices\FPGA Addon\ Windows\Quick Start Documentation (Year)\Custom Devices\FPGA Addon\Windows\Quick Start Documentation