VeriStand Loop Rate Slowed Down After Adding cDAQ Device to System Definition

Updated Apr 10, 2020

Issue Details

I have a VeriStand project where the Primary Control Loop is configured to run at a fast rate, such as 100 Hz. I would like to add a CompactDAQ (cDAQ) chassis and module to my project. However, when I add the chassis and module to my System Definition File (SDF), my loop rate is slowed down considerably. Why is this and how do I ensure my loop can run at rate I specify?


One of the first operations performed by the VeriStand Primary Control Loop (PCL) is to read single-point data from any DAQ hardware configured in the SDF. cDAQ devices do not support hardware-timed single-point mode, so if you are using a cDAQ in your VeriStand project, the single-point read is going to be software-timed. This can introduce some latency into the read operation and will be less deterministic than if you were using a hardware-timed single-point (HWTSP) device.

In addition, if the maximum sample rate of the module in your cDAQ chassis is slower than the PCL rate, then it will force the PCL rate to wait until a sample is returned from the module before it can iterate. For example, the NI 9211 is a thermocouple module with a maximum sample rate of 14 samples/s. Even if you configure the PCL to run at 100 Hz, if you try to add this module to the System Definition, your PCL will not be able to run faster than 14 Hz since it is dependent on data from the module.

To avoid this, only use DAQ devices with sample rates higher than your PCL rate. In addition, you will see increased performance by only using devices compatible with hardware-timed single-point mode.

If you must use a cDAQ chassis and modules with lower sample rates in VeriStand, you can create either acquire the data as analog waveforms rather than single-point values, or you can create a asynchronous VeriStand Custom Device to take data from the slower devices.