This tutorial provides an introduction to logging data to disk with CompactRIO in addition to an overview of the CompactRIO architecture and programming models available in LabVIEW.
CompactRIO is powered by NI LabVIEW FPGA and LabVIEW Real-Time technologies, giving engineers the ability to design, program, and customize the CompactRIO System with easy-to-use graphical programming tools.CompactRIO combines an embedded real-time processor, a high-performance FPGA, and hot-swappable I/O modules. Each I/O module is connected directly to the FPGA, providing low-level customization of timing and I/O signal processing. The FPGA is connected to the embedded real-time processor via a high-speed PCI or AXI bus. This represents a low-cost architecture with open access to low-level hardware resources. LabVIEW contains built-in data transfer mechanisms to pass data from the I/O modules to the FPGA and also from the FPGA to the embedded processor for real-time analysis, post processing, data logging, or communication to other distributed targets or computers.
Figure 1. LabVIEW RIO Architecture
The CompactRIO System features industrial processors that deterministically execute your LabVIEW Real-Time applications on the reliable NI Linux Real-Time or Wind River VxWorks real-time operating system. LabVIEW has built-in functions for transferring data between the FPGA and the real-time processor within the CompactRIO System. Choose from more than 600 built-in LabVIEW functions to build your multithreaded embedded system for real-time control, analysis, data logging, and communication. You can also integrate existing C/C++ code with LabVIEW Real-Time code to save on development time.
The embedded FPGA is a high-performance, reconfigurable chip that engineers can program with LabVIEW FPGA tools. Traditionally, FPGA designers were forced to learn and use complex design languages such as VHDL to program FPGAs. Now, any engineer or scientist can use graphical LabVIEW tools to program and customize FPGAs. Using the FPGA hardware embedded in CompactRIO, you can implement custom timing, triggering, synchronization, control, and signal processing for your analog and digital I/O. You can also bring existing VHDL or Verilog IP into LabVIEW FPGA to save on development time.
A variety of I/O types are available including voltage, current, thermocouple, RTD, accelerometer, and strain gauge inputs; up to ±60 V simultaneous-sampling analog I/O; 12, 24, and 48 V industrial digital I/O; 5 V/TTL digital I/O; counter/timers; pulse generation; and high voltage/current relays. Because the modules contain built-in signal conditioning for extended voltage ranges or industrial signal types, you can usually connect wires directly from the C Series Modules to your sensors and actuators.
Begin by creating a new project in LabVIEW, where you will manage your code and hardware resources.
Create a new project in LabVIEW by selecting File » New Project
Adding your CompactRIO system to the project by right-clicking on the Project item at the top of the tree and select New » Targets and Devices… This dialog allows you to discover systems on your network or add offline systems.
Figure 2. Add new targets and devices to your LabVIEW project.
Expand the Real-Time CompactRIO folder, select your system.
Note: If your system is not listed, LabVIEW could not detect it on the network. Ensure that your system is properly configured with a valid IP address in Measurement & Automation Explorer (MAX). If your system is on a remote subnet, you can also select to manually enter the IP address.
Figure 3. Expand and select your existing CompactRIO Real-Time System
LabVIEW provides two programming modes for CompactRIO Systems. If you have LabVIEW Real-Time and LabVIEW FPGA on your development computer, you will be prompted to select which programming model you would like to use. You can change this setting later in the LabVIEW Project if needed. Select the appropriate programming model for your application.Note: You can change the programming mode later if needed using the CompactRIO Chassis Properties dialog box.Scan Interface (CompactRIO Scan Mode) - This option allows you to program the real-time processor of your CompactRIO System and access the I/O without needing to program the FPGA. In this mode, NI provides a pre-defined personality for the FPGA that periodically scans the I/O and places it in a memory map, making it available to LabVIEW Real-Time. CompactRIO Scan Mode is sufficient for applications that require single-point access to I/O at rates approaching one kilohertz. To learn more about scan mode, read the Using CompactRIO Scan Mode with NI LabVIEW white paper and follow Take Your First Measurement in LabVIEW Real-Time (Data Logging).LabVIEW FPGA Interface - This option allows you to unlock the real power of CompactRIO by customizing the FPGA personality in addition to programming the real-time processor, achieving performance that would typically require custom hardware. Using LabVIEW FPGA, you can implement custom timing and triggering, off-load signal processing and analysis, create custom protocols, and access and control I/O at its maximum rate.
Figure 4. LabVIEW FPGA Interface Mode to use C Series Modules directly from LabVIEW FPGALabVIEW will now attempt to detect the chassis and C Series I/O Modules present in your system and automatically add them to the LabVIEW Project. Note: If your system was not discovered and you choose to add it offline, you will need to add the chassis and C Series I/O manually. This document discusses this process for scan mode and FPGA mode.Once your system has been added to the LabVIEW Project, proceed to either the LabVIEW FPGA Interface Tutorial below or the CompactRIO Scan Interface Tutorial, depending on which programming mode you selected.
This section will walk you through creating a basic high-speed data logging application on CompactRIO using LabVIEW FPGA. Follow You should now have a new LabVIEW Project that contains your CompactRIO System, including the controller, chassis, FPGA, and C Series I/O Modules. In this tutorial we will be using an NI 9205 analog input module; however, the process can be followed for any analog input module. You can also download the solution from the Attachments section of this article.
Save the project by selecting File»Save and entering Basic logging with LabVIEW FPGA. Click OK.
In the LabVIEW Project, expand the CompactRIO Controller and chassis to find the FPGA item. Right-click on the FPGA item and select New»VI. This VI will perform the high-speed analog acquisition.
Figure 5. Create a new VI underneath the recently added FPGA target
Save the VI as FPGA.vi
Expand the folder named Mod1 and drag Mod1/AI0 to the FPGA VI diagram. To add an I/O node that will acquire a sample from the analog input module
Figure 6. Drag and Drop IO Modules to the LabVIEW Block Diagram
Figure 7. Expand the I/O node in order to access multiple analog inputs
Figure 8. Add a for loop to read out each input
To create the FIFO that will pass data from the FPGA VI to the real-time VI, right-click on the FPGA in the LabVIEW Project and select New»FIFO.
Figure 9. Add a new FPGA FIFO underneath the LabVIEW Target
Configure the FIFO as shown. This information was obtained by using the Context Help information on the wire returning data from the NI 9205 I/O node on the FPGA VI diagram.
Type: Target to Host – DMAData Type: FXPEncoding: SignedWord length: 26 bitsInteger word length: 5 bits
Figure 10. Configure FIFO using FIFO Properties
Drag and drop the FIFO into the For Loop on your FPGA diagram.
Figure 11. Drag and Drop the FIFO into the For Loop
Wire the auto-indexed array terminal into the Element input of the FIFO. Create a constant for the Timeout input of the FIFO with a value of 0.
Wire the Timed Out? output of the FIFO into an Or function. Create an indicator for the result of the Or function and name it Overflow?
Place a Feedback Node on the diagram and wire the result of the Or function to its input (right side). Wire the output (left side) of the feedback node to the remaining input of the Or function. Create a false constant for the initialization input of the feedback node. The result, shown below, creates a latching mechanism that will cause Overflow? to become True and stay True, if the Timed Out? output of the FIFO is ever asserted. This output indicates that the FIFO was full and data was lost.
Figure 12. Place a Feedback Node into the For Loop
To enforce execution order and timing on the diagram, place a Flat Sequence Structure around the diagram and add one additional frame after as shown.
Figure 13. Add a Flat Sequence Structure around the existing code
Place a Loop Timer in the right-hand frame. Select uSec from the Configure Loop Timer dialog
Create a control for the Loop Timer input.
Figure 14. Determine Loop timer by changing the Counter Units
Place a While Loop around the Flat Sequence Structure and create a False constant for the loop stop condition. Congratulations! You have completed the FPGA VI, which needs to be compiled into a bit stream that will be downloaded onto the FPGA. In order to begin the compilation process.
Figure 15. Add a While Loop in order to add each element into the FIFO
Save the VI and then right-click on the VI in the LabVIEW Project and select Compile.
Figure 16. Compile the FPGA code by right clicking on the FPGA VI
In the LabVIEW Project, right-click on the CompactRIO Controller and select New»VI. Once LabVIEW finishes generating intermediate files, you can minimize the compilation process and begin writing the LabVIEW Real-Time VI. This VI will run on the real-time controller and continuously read data out of the FIFO set up between the FPGA and processor. The data will then be written to disk for offline analysis.
Figure 17. Add a new VI underneath your CompactRIO Controller
Save the VI as RT.vi
From the FPGA Interface palette, place an Open FPGA VI Reference on the RT.vi block diagram and double-click on it.
Select VI»FPGA.vi and uncheck Run the FPGA VI. This configuration will cause the function to download the FPGA VI, but not begin executing it.
Figure 18. Configure Open FPGA VI Reference
From the FPGA Interface palette, select Invoke Method and place it on the diagram. Wire the outputs of the Open FPGA VI Reference to the inputs of the Invoke Method.
Left-click on Method and select FIFO»Start. This function will initialize the DMA engine, which is powering the FIFO that between the processor and the FPGA.
Figure 19. Select the Method for the FIFO using Invoke Node
From the FPGA Interface palette, place a Read/Write Control function on the diagram. Connect the reference and error cluster wires. This function allows you to read and write to the controls and indicators on the FPGA VI.
On the Read/Write Control, left-click Unselected and select Count(uSec). This corresponds to the Count(uSec) control on the FPGA VI front panel.
Figure 20. Accessing Read/Write control on the FPGA VI
Create a control for the Count(uSec) input. This control will be used to set the analog input acquisition rate in microseconds. Enter a value of 500 for the Count(uSec) control on the front panel to set an acquisition rate of 2kHz.
Place a TDMS Open VI on the diagram. Create constants for the file path and operation inputs. Enter analog_input.tdms for the file name and select create or replace for the operation. Wire the error cluster from the Read/Write Control to TDMS Open. This function will create a new TDMS file where the data will be logged.
Figure 21. TDMS Logging functionalityNote In case your CompactRIO Controller is running a different Real-Time OS choose the appropriate file path shown below. Please see Real-Time Controllers and Real-Time Operating Systems Compatibility for more information.
Figure 22. Using the right file path depending on the CompactRIO Controller that is used
Place another Invoke Method function on the diagram and select the Run method. Wire it as shown. The Run method causes the FPGA VI to begin executing. The code written so far downloads your FPGA VI, starts the DMA engine to prepare for high-speed data transfer through the FIFO, sets the acquisition loop rate on the FPGA, creates a new file for logging, and then starts the FPGA VI. Next, you will write the code to continuously read data from the FIFO and write it to disk.
Figure 23. Adding Run Method in order to execute the LabVIEW FPGA code
Place a while loop to the right of the existing code and place an Invoke Method function, from the FPGA Interface palette, in the while loop.
Wire the FPGA VI Reference Out and error out terminals of the Run method to the Invoke Method inputs.
Left-click Method and select FIFO»Read.
Figure 24. Read FIFO values within the While Loop
Figure 25. Configure the Number of Elements and FIFO Timeout
A snippet of code is provided to perform the data logging and stop condition for the while loop. You can either drag and drop the image below to your block diagram or download the code here and copy and paste its contents to your diagram.
Drag and drop this VI Snippet to your block diagram
Connect the provided code snippet to your diagram as shown below.
Wire the tdms file out reference of the TDMS Open VI to the tdms file input of the TDMS Write
Wire the FPGA VI Reference Out output of the FIFO.Read function to the FPGA VI Reference In input of the Overwrite? function.
Wire the error out output of the FIFO.Read function to the error in input of the TDMS Write.
Wire the Data output of the FIFO.Read function to the number input of the To Double Precision Float function.
Wire the result output of the Compound Arithmetic OR function to the stop condition of the while loop.
Place a Wait (ms) function in the while loop and create a constant with a value of 5 for the milliseconds to wait input. This introduces some sleep time for the processor to perform other tasks each iteration. The while loop will now continuously read data from the FIFO, format it, write it to the TDMS file, display it on a waveform chart, and then check to see if the overflow condition on the FPGA VI is true. The while loop will stop if the stop button is pressed, an error occurs, or if the overflow condition is met. To complete the application, you will add code to close the TDMS File and FPGA VI.
Figure 26. Final Code Example in LabVIEW Real-Time using FPGA VI Reference
Place a TDMS Close VI and a Close FPGA VI Reference VI outside of the while loop and wire the file reference, FPGA reference, and error clusters as shown.
Figure 27. Close FPGA IV Reference
Click Run on RT.vi, click Save for any unsaved items, and click OK on any dialogs or warnings about applying changes to the CompactRIO System. LabVIEW will now deploy your VI over Ethernet to run embedded on the CompactRIO System.
Once the VI deploys and begins running, view the front panel of your VI to see the current I/O values plotted on the waveform chart.
Figure 28. Finished LabVIEW Front Panel showing logging data
Complete the following steps to retrieve and view the data logged on the CompactRIO System:
Using Windows Explorer or a Web browser, navigate to ftp://<ip address> where <ip address> is the IP address of your CompactRIO System
Download tempdata.tdms (or whatever you named the TDMS file)
If you have Microsoft Excel, you can view TDMS files by selecting the Add-Ins tab and clicking the TDM Importer. The first page of the workbook contains file information and the remaining sheets contain the channel data. The TDM Importer installs with LabVIEW by default; however, if the TDM Importer is not present, you can install it from here.
Figure 29. Install TMD Importer in order to open the tdms files directly in Excel
Note: NI also supports WebDAV (Web Distributed Authoring and Versioning). It’s a great secure alternative to exchange files using a standard web browser. Please see Using WebDAV to Transfer Files to and from your Real-Time Target for more information.
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