I have a LabVIEW project for myRIO-1900. In there, I created a simple FPGA which reads the voltage for the A/AI0. I can run this VI and it works fine. The bitfile created for this FPGA VI is called FPGAbitfile.
Now, I want to read the A/AI1 from my RT VI. When I run my RT VI, everything works fine. Here is how my RT and FPGA VIs look like:
The next step is to modify my RT VI in order to call the FPGA modified personality (FPGAbitfile
) through the Open FPGA VI Reference
function as shown in the following figure:
After running this VI, the error -61202 appears after the Smart Open.vi:
As an additional note, the Open FPGA VI Reference
function points to the bitfile created for the FPGA VI. How can I fix this?