Error -61202 Modifying the FPGA Personality of myRIO-1900

Issue Details

I have a LabVIEW project for myRIO-1900. In there, I created a simple FPGA which reads the voltage for the A/AI0. I can run this VI and it works fine. The bitfile created for this FPGA VI is called FPGAbitfile. Now, I want to read the A/AI1 from my RT VI. When I run my RT VI, everything works fine. Here is how my RT and FPGA VIs look like: 
The next step is to modify my RT VI in order to call the FPGA modified personality (FPGAbitfile) through the Open FPGA VI Reference function as shown in the following figure:

After running this VI, the error -61202 appears after the Smart Open.vi:  As an additional note, the Open FPGA VI Reference function points to the bitfile created for the FPGA VI. How can I fix this?
 

Solution

This problem can be seen when trying to multiple FPGA references at the same time. myRIO-1900 has a default FPGA biftile or personality that is used by the Smart Open.vi. If you need to use a custom FPGA personality, then you need to make use of the function  Set Custom Bitfile.vi. This function needs to be used at the beginning of your code so the rest of the functions that require access the FPGA personality (as Smart Open.vi) can use the customized version instead of the default version.

When the Set Custom Bitfile.vi is executed the new FPGA personality will be defined. In this case, defining the right execution order using the error cable will fix the issue. You can connect the output error cable of the Set Custom Bitfile.vi to the input of the Smart Open.vi as shown below.