Two of the most commonly used hardware description languages are VHDL and Verilog. LabVIEW FPGA only supports native integration of third party IP written in VHDL. However, it is possible to integrate IP written in Verilog by following the procedures outlined in this tutorial.
This tutorial shows how to use Xilinx ISE Design Suite to prepare Verilog modules for integration into LabVIEW FPGA by using the following procedures:
The attached file "verilog_integration_tut.zip" contains the tutorial (in PDF format) along with some example HDL files and a completed LabVIEW project.
Download and extract the attached file: "verilog_integration_tut.zip".
Open "Preparing Verilog Modules For Integration Into LabVIEW FPGA.pdf" and follow the contained procedure.
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