The CLIP Node is a framework for importing existing FPGA IP into LabVIEW FPGA hardware and communicating to it through the LabVIEW FPGA diagram. Once imported, the IP runs independently in parallel with LabVIEW FPGA VI execution. The IP can be in the form of either VHDL or intermediate files such as electronic design interchange format (EDIF) netlists. This feature targets users with some digital design experience and basic knowledge of VHDL, because the IP imported is often written in a lower-level hardware description language ( HDL).
Support for CLIP varies by FPGA target. Refer to the target hardware documentation for information about CLIP support. Some FPGA targets work with one or both of the following types of CLIP:
User-defined CLIP − Import VHDL code to communicate directly with an FPGA VI.
Socketed CLIP − Import VHDL code to communicate directly with an FPGA VI and with FPGA pins that are not directly exposed to the LabVIEW FPGA Module. Some FPGA targets define a fixed-CLIP socket in the FPGA where you can insert socketed CLIP.
Figure 1. Imported VHDL code in user-defined CLIP Nodes can communicate with an FPGA VI, whereas a socketed CLIP Node allows the IP to interface with both the FPGA VI and available FPGA pins.
For the most up-to-date information, refer to the LabVIEW FPGA Module Help topic titled Using VHDL Code as Component-Level IP (FPGA Module).
The following steps outline the procedure for using CLIP in an FPGA application:
To add CLIP to an FPGA target, you must provide IP in the form of VHDL code to compile into the FPGA target. You can provide the VHDL code in the following ways:
Note: More than 50 Xilinx IP blocks are in the CORE Generator IP palette in LabVIEW FPGA, which you can incorporate into the dataflow of your LabVIEW FPGA VI without the need to import it using the CLIP or IP Integration Node.
Learn how to Increase IP Reuse With the Xilinx CORE Generator IP Palette.
An important consideration when using CLIP Nodes is the data types supported in LabVIEW FPGA and how they translate to VHDL data types. If your IP uses a logic vector that is not one of the data types listed in Table 1, you need to write a wrapper to extend, cut off, or break up the standard LabVIEW types to fit the data widths of the IP.
Refer to the LabVIEW FPGA Module Help to learn more about other considerations for your IP including using external clocks, crossing clock domains, using synchronization registers, implementing asynchronous resets, and working with constraints and hierarchy.
std_logic_vector(x downto 0)
where x is in range [0,63].
Note: The following example uses the attached simple_and.vhd file to demonstrate how to import IP into a user-defined CLIP Node.
To map the IP inputs and outputs to I/O in LabVIEW, use the FPGA Target Properties Wizard to create an XML file that defines the necessary characteristics of the IP. Follow the steps below to complete this task.
Declaring the CLIP within the FPGA does not actually add it to the project because you can instantiate multiple instances of one CLIP on the same FPGA. In the next step, you will create an instance of the previously declared simple AND CLIP item.
Note: The IP Integration Node example imports the attached demo_adder.vhd IP block.
The CLIP and IP Integration Nodes are two ways to import external IP into and you should select between these import methods based on your application. The CLIP Node executes independently and in parallel with your IP developed in LabVIEW FPGA. In addition, CLIP can interface directly with the FPGA clocks and I/O pins. In contrast, the IP Integration Node is inserted into the LabVIEW FPGA block diagram and executes as defined by the dataflow of the LabVIEW VI. As part of the LabVIEW dataflow execution, the IP integration Node gives you the ability to verify the overall application behavior and timing using the cycle-accurate simulation tools.
For more details on the differences between CLIP and the IP Integration Node, refer to the Integrating Third-Party IP (FPGA Module) topic in the LabVIEW Help.
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