Can I Convert My NI LabVIEW FPGA VI Into VHDL Code?

Updated Jun 19, 2020

Reported In


  • LabVIEW FPGA IP Export Utility
  • LabVIEW FPGA Module

Issue Details

I have written and tested my FPGA algorithm in LabVIEW using NI FPGA Module and NI FPGA Hardware. I want to deploy this algorithm on other Xilinx FPGAs. How can I convert my FPGA VI to VHDL code to integrate with Vivado Design Suite?


An FPGA VI can be exported as an encrypted netlist or plaintext VHDL code using the NI LabVIEW FPGA IP Export Utility.
This utility can be used to export your algorithm which can be integrated into your Vivado project and can be used on any Xilinx FPGA device of the same family. For example, an FPGA VI for sbRIO-9627 (uses Zynq-7020 SoC) can be exported into VHDL code and subsequently be integrated it into a Vivado Design Suite project for any Xilinx Zync-7000 series SoC.

Additional Information

While most nodes available on the LabVIEW FPGA palette can be used as building blocks for the algorithm, the following nodes or features cannot be used: 
  • Nodes that access external resources of FPGA chip:
    • DMA FIFO 
    • Peer-to-Peer (P2P) FIFO
    • DRAM Memory o I/O nodes
    • Interrupt o
    • User-Defined Variable
  • User-defined component level IP (CLIP)
  • Local variables in the top-level FPGA VI. You can use local variables in non top-level VIs.