Routing PXI Trigger Lines for the PXIe-6593/6594 in LabVIEW FPGA Module

In this article, you will learn how to send trigger signals across the backplane of a PXI(e) chassis using the PXIe-6593/6594 High-Speed Serial modules.

There are two different configurations we can work with:

1. Receiving external triggers from a timing Module
2. Use the Backplane DSTAR triggers to interact with other Modules

Depending on the scenario you will need to use the associated Routing CLIP that is shipped with the NI-FlexRIO driver. The Routing CLIP is a large multiplexer that connects the PXI trigger lines to the FPGA diagram through the Source and Destination IO nodes.

The Routing CLIP is used to send a trigger signal from the module to other devices in the chassis via the PXI_Trig lines on the backplane. It includes 32 Source and 32 Destination I/O items. Signals you want to send to another device through the trigger lines can be sent to "Source" I/O, and signals to read can be read from "Destination" I/O. To use this CLIP, you will need to configure both the Host side using the NI-FlexRIO Route Signals VI and the FPGA side using the FPGA I/O nodes. 

If you have a PXIe-6674T Timing & Synchronization module you can also utilize the DStarB and DStarC lines that are accessible to the PXIe-6593/6594 to send other trigger and clock signals across the chassis backplane, which are both available as FPGA I/O items, without needing to use the Routing CLIP. 

This article will take you step-by-step through how to implement the Routing CLIP in your LabVIEW FPGA project. The LabVIEW FPGA project template being used in this article is from the Getting Started FlexRIO Integrated IO.vi tool found in the NI Example Finder under the folder Hardware Input and Output > FlexRIO > Integrated IO > Getting Started > Getting Started FlexRIO Integrated IO.vi > High-speed Serial  >  PXIe-659X (KU0X0 - CLIP Template.

Important Considerations on the Routing CLIP

On the driving 6593's FPGA diagram, you can generate the pulse and attach it to one of the Routing Source I/O nodes. It doesn't matter which source node, but we can be simple and say Source1 for this example. On the receiving module's FPGA diagram, you can drop one of the Routing Destination I/O nodes and use that to read the pulse. Again, it doesn't matter which destination node you use, but for this example, we'll say it's Destination1. While these signals are now connected to the Routing CLIP, they are not designated to any specific trigger line yet.

On the Host side, the job of Route Signals VI is to tell the driver that you want to connect these two signals across the two devices. If the driving device is on PXI1Slot2, and the receiving device is on PXI1Slot3, then you call the Route Signals VI with /PXI1Slot2/Source1 as the source, and /PXI1Slot3/Destination1 as the destination. The driver will then select a trigger line that is not being used, and configure the Routing CLIP of the driving device to send the Source1 signal onto whichever trigger line it selected.

It will likewise configure the Routing CLIP of the receiving device to send that trigger line to the Destination1 signal. Which trigger line is picked depends on what else is using trigger lines, so it may not be consistent. If you need to send a signal to a specific trigger line, you can drive that signal into any of the Source nodes, just like before. Then when configuring the routing using Route Signal VI, the source is the same as above, but the destination is simply PXI_Trig0 (or 1, or 2, etc). This will force the driver to configure the Routing CLIP to send the desired Source node into the required trigger line.

For this task, you will require the following:

• Hardware
  • PXIe-6593 or PXIe-6594
  • Optional: PXIe-6674T Timing & Synchronization module
• Software
  • LabVIEW version 2016 or greater
  • LabVIEW FPGA Module version 2016 or greater
  • NI-FlexRIO Driver - version 19.6 or greater
• Prerequisite Knowledge
  • LabVIEW FPGA Course

Configuration of the DStarB and DStarC

1. Open a LabVIEW Project that has the FPGA Target, the definition of the FPGA I/O Node, and the Socketed CLIP configuration define
   1. It is recommended to start always with the shipped examples since all of these configurations are already done
   2. The LabVIEW FPGA project template being used in this article is from the Getting Started FlexRIO Integrated IO.vi tool found in the NI Example Finder under the folder Hardware Input and Output > FlexRIO > Integrated IO > Getting Started > Getting Started FlexRIO Integrated IO.vi > High-speed Serial  >  PXIe-659X (KU0X0) - CLIP Template.
   3. Click on the example and the view of the Project Tree will:
      1. 
2. Adding the DStar Lines to the project as FPGA I/O:
   1. Right-click the FPGA Target
   2. Then go to New->FPGA I/O
      1. 
   3.  Under PXI you can add PXIe_DStarB and PXIe_DStarD
      1. Click in the  PXIe_DStarB
      2. Click on the blue arrow that displays add
         1. 
      3. Repeat if PXIe_DStarD is required for your application
   4. Click in OK 
   5. Now we define the FPGA I/O and we have access to the PXI Dstar trigger lines

Configuration of the Routing CLIP in the Target Host and FPGA Target:

The following steps will demonstrate how to send a trigger signal from a PXIe-6593 module to a specific destination using the Routing CLIP. 

1. Open the block diagram of the FPGA VI under the target and place an FPGA I/O node down for the Routing Source. You can either drag and drop the Source I/O node from the LabVIEW project under the Routing CLIP or place an FPGA I/O node from the functions palette and change the element to Routing > Source1.  

2. Open the block diagram of the Host VI and place the NI-FlexRIO Route Signals VI down. For the source, put in resource name for the driving module followed by the source number. For the destination, put in resource name for the receiving module followed by the destination number.

3. On the block diagram of the FPGA VI for the receiving device place another FPGA I/O node down for the Routing Destination. You can either drag and drop the Destination I/O node from the LabVIEW project under the Routing CLIP or place an FPGA I/O node from the functions palette and change the element to Routing > Destination1.

Configuration to send a trigger signal from a PXIe-6593 module to a specific PXI_Trig line using the Routing CLIP. 

1. Open the block diagram of the FPGA VI under the target and place an FPGA I/O node down for the Routing Source. You can either drag and drop the Source I/O node from the LabVIEW project under the Routing CLIP or place an FPGA I/O node from the functions palette and change the element to Routing > Source1.  

2. Open the block diagram of the Host VI and place the NI-FlexRIO Route Signals VI down. For the source, put in the resource name for the driving module followed by the specific PXI_Trig line.

The input and output data types to the Routing\Source FPGA I/O node are a boolean data type to show the high or low trigger pulse. This is what is actually controlling the trigger pulse to go high or low from the 6593/4 to the PXI_Trig trigger lines.