Understanding CLIP Source Files Provided Along NI PXIe-6593R Shipping Example

Updated Dec 5, 2023

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The below table provides a short description of all the files available in the CLIP folder of NI PXIe-6593 Aroura 64b66b shipping example project:

File Name	Description
UserRTL_PXIe6593_Aurora64b66b_Streaming.vhd	Top-level of CLIP VHDL file
PXIe6593_Aurora64b66b_Streaming.xml	CLIP XML defining files and CLIP IO (understandable by LabVIEW FPGA)
PXIe6593_Aurora64b66bClip_2x4Lanes.xdc	CLIP constraints (Xilinx design constraint file with timing and IO constraints)
Ni6593FixedLogic.dcp	Configuration netlist to configure MGT reference clocks. This netlist is required for all (default or user-defined) CLIPs implementing any protocol. You cannot remove this netlist during modifications.
aurora_64b66b_DS.xci	Xilinx Aroura 64b66b CoreGen IP
aurora_64b66b_DS.edf	The aurora_64b66b_DS.xci was synthesized to generate this netlist/EDIF.
AXI4Lite_GTHE3_Control_Regs4.edf, PkgAXI4Lite_GTHE3_Control.vhd	AXI registers to connect to Aurora's MGT status and control ports. These are not Aurora-specific and can be connected to any MGT IP on the NI PXIe-6593.
MgtTest_DRP_bridge.vhd, PXIe659XR_AXI4_Lite_Address_Map.vhd, AXI4_Lite_to_DRP.vhd	Converts AXI to DRP to access DRP registers in transceivers. These are also not Aurora specific and can be connected to any MGT IP on the NI PXIe-6593

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