AXI4_Lite/DRP IP in NI High-Speed Serial Instrument Shipping Examples

Updated Dec 5, 2023

Reported In

Hardware

  • PXIe-6593
  • PXIe-6594
  • PCIe-6593

Issue Details

Can I understand why NI High-Speed Serial devices such as the PXIe-6593R shipping example have IPs related to AXI4_Lite and DRP? What is their use? If I need to modify the default CLIP to make changes in the provided 64b66b protocol or to implement a different protocol (for instance 8b10b), how should I deal with these IPs specifically?
 

Solution

DRP stands for dynamic reconfiguration port. As the name suggests, the AXI and DRP files are used for dynamically reconfiguring the high-speed serial transceivers from the host without making any FPGA code changes (which would otherwise require a recompile every time). These IPs can also be used by the NI FlexRIO APIs to run an eye scan.
Please note that these IPs are not necessary for the CLIP to run, so they can be removed, and users can just have Aurora protocol running at its default configuration.

 

Additional Information

  • If a user decides to remove them, all the related ports from the VHDL port map, CLIP XML, and the instruction framework on the NI LabVIEW FPGA diagram must also be deleted along.
  • Modifying the default CLIPs of NI High-Speed Serial Instruments needs significant Xilinx Vivado and VHDL expertise.

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