Recompiling LabVIEW FPGA Examples With Licensed Xilinx CORE Generator IP Blocks

Updated Oct 18, 2023

Reported In

Software

  • LabVIEW FPGA Module
  • FPGA Xilinx Compilation Tools

Issue Details

I plan to modify and recompile a LabVIEW FPGA example that uses licensed Xilinx Core Generator IP block(s). Do I need a valid Xilinx license for the IP(s) every time I recompile any such example?
 

Solution

LabVIEW FPGA users can import Xilinx Core Generator IP blocks inside LabVIEW FPGA VI. Some of these IPs need a license. For successful compilation, any required license has to be valid each time when FPGA code is recompiled. The license can be purchased directly from Xilinx.

Additional Information

Once purchased from Xilinx, the license can be loaded to Vivado License Manager (VLM). The VLM can be invoked from C:\NIFPGA\programs\Vivado<version>\bin\vlm.bat.
Once VLM loads, click Get License>>Load License and select Copy License. In the Select License File dialog, navigate to the license file provided by Xilinx. Select the license file and click Open. The license should now be successfully loaded.

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To check the license status, click View License Status under Manage License. 

Alternatively, place the .lic file in one of the following default directories, depending on your specific FPGA target:
  • (Xilinx ISE) C:\NIFPGA\programs\XilinxY_Z\ISE\coregen\core_licenses, where XilinxY_Z is the current version of the Xilinx compilation tool for ISE for your FPGA target.
  • (Xilinx Vivado) C:\NIFPGA\programs\VivadoA_B\data\ip\core_licenses, where VivadoA_B is the current version of the Xilinx compilation tool for Vivado for your FPGA target.

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