Configure LabVIEW FPGA Floating-Point VI to Use as Natural Logarithm Operator

Updated Aug 10, 2022

Environment

Software

  • LabVIEW FPGA Module

The purpose of this Knowledge Base article is to explain the process to follow to create a VI that performs a Natural Logarithm Function using the LogiCORE IP Floating-Point Operator from Xilinx in LabVIEW FPGA

The steps are the following:
  1. Place the Floating-Point VI on the FPGA Block Diagram:
Step1.JPG
  1. Save the VI and double-click on it, then select Configure Xilinx IP:
step2.png
  1. In the Select Logarithm Operation Selection tab select Logarithm:
step3.JPG
  1. Then go to the Interface Options tab and select NonBlocking as the Flow Control option:
step4.JPG
According to the LogiCORE IP Product Guide, the term Non-Blocking option means that the lack of data on one input channel does not block the execution of an operation if data is received on another input channel. Refer to that Product Guide for more information about these settings.
  1. Then click OK and wait for the IP Generation Process to complete.
step5.png
  1. Once that process is completed, click Next to continue with the configuration of the Xilinx Floating Point function.
  2. On the Clock and Enable Signals window, set the Clock signal Name as aclk and select the s_axis_a_tvalid from the IP Enable Signals:
step7.JPG
This is because, when all of the present input channels receive an active TVALID, an operation is validated and the output TVALID is asserted to qualify the result (after the delay configured for the latency of the core has elapsed). Please refer to the Product Guide for more information on this.
  1. Click Next and in the Reset Signals and Behavior window, for the purpose of this example, set the Asynchronous reset signal as No Asynchronous Reset and click Next:
step8.JPG
  1. In the IP Terminals window, for the purpose of this example and to get a more readable result, change the data type from Fixed-point (default) to Single-Precision:
step9.JPG
  1. Click Finish to close the Xilinx Floating-Point Node Properties window.
 

Now, the Floating-Point Operator has a 22 cycles latency so it has to run in a timed loop and you must connect a boolean value to the s_axis_a_tvalid input in order to validate the operation, so create a Timed-Loop around the Floating-Point Operator and wire up the inputs and outputs of the function as shown in the following code snippet:
Result Snippet.png
As mentioned above, the m_axis_result_tvalid will be asserted once the operation is validated so this is used as the stop signal for the Timed Loop in this example.
Now this example can be run on the FPGA target or simulation mode.
 

The following is an example of running this function in simulation mode for the operation ln(5), which result can be validated using the Windows built-in calculator:
Result.JPG
 

Next Steps

For using this example on the FPGA or your target check the Product Guide for each version of the LogiCORE IP Floating-Point Operator which lists the supported device family.
This same process can be followed to achieve a different operation supported by the function, like exponential.

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