Follow the steps below to configure a Host VI that reads and writes simulated data to simulated FPGA modules:
Note: The steps below refer to a cRIO, but the same method can be applied to other FPGA Targets.
1. Refer to
Simulate FPGA Targets Using the Project Explorer with LabVIEW to set up a simulated cRIO and FPGA in a LabVIEW project.
- For demonstration purposes, this example utilises a cRIO-9030 with a NI-9205 module.
2. Right click on the
FPGA Target and select
New >> VI.
- Save this VI as "FPGA VI".
3. In the FPGA VI, place a
While Loop with some basic timing.
- All that's required in this VI is a continuously running loop. The FPGA should resemble the following image.
Note: This image is a LabVIEW snippet, which includes LabVIEW code that you can reuse in your project. To use a snippet, right-click the image, save it to your computer, and drag the file onto your LabVIEW diagram.
4. Right-click on the
My Computer item in the project tree and select
New >> VI.
- Save this VI as "Host VI".
5. In the Host VI, place a
While Loop with some basic timing. Connect a
Boolean Control to the stop condition.
- For demonstration purposes, the While Loop shown uses the Wait (ms) function to force each iteration to take 10 milli-seconds.
6. From the
Functions Palette, navigate to
FPGA Interface and place a
FPGA Desktop Execution Node inside the
While Loop.
7. In the
Configure FPGA Desktop Execution Node pop-up, select the
Browse Project button and select the FPGA VI from within the project.
8. In the
Available Resources section, expand the
FPGA Target until the required module input/output can be seen.
9. Select the desired input(s) or output(s) and click the blue arrow pointing towards the right.
- Once complete, the configuration window will appear similarly to the below image.
10. Click on the input or output under
Selected Resources and change the terminal direction as required.
- To write simulated data to the terminal, select In for Change Terminal Direction.
- To only read data from the terminal, select Out for Change Terminal Direction. Note: simulated modules will produce noise or unexpected data if nothing is written to them.
- To both read and write data, select In/Out for Change Terminal Direction.
11. Click
OK to close the configuration window.
12. Use any preferred method to create simulated data points and wire this to the module input of the
FPGA Desktop Execution Node.
- For demonstration purposes, this example generates a sinusoidal waveform by using the Sine Wave VI from the Signal Generation Palette. The While Loop incrementally indexes each element in the sine wave array and writes the current element to the FPGA module.
13. To read the module data back out and display it on a
Waveform Chart:
- Place a Build Array function on the module output of the FPGA Desktop Execution Node.
- On the Front Panel, navigate to Graphs >> Waveform Chart in the Controls Palette. Place down a Waveform Chart.
- Connect the Waveform Chart Indicator to the Build Array output.
- The Host VI should now resemble the following image.
Note: This image is a LabVIEW snippet, which includes LabVIEW code that you can reuse in your project. To use a snippet, right-click the image, save it to your computer, and drag the file onto your LabVIEW diagram.
14. Run the Host VI and observe that the
Waveform Chart populates with the simulated data.