Using the Native FPGA in VeriStand

The FPGA Addon Custom Device allows users to access an existing FPGA bitfile in VeriStand with little or no modification. NI recommends you use the FPGA Addon Custom Device if you don't have the requirement of synchronizing data acquisition/generation with the VeriStand Primary Control Loop (PCL). If you have this requirement and want to use the FPGA as a timing source for the PCL, you must use the native VeriStand FPGA. This article explains how to use NI FPGA devices (CompactRIO, R Series Multifunction RIO) in the native VeriStand FPGA.

Prerequisites

Before starting this tutorial, ensure that you have completed Getting Started With NI FPGA Devices in NI VeriStand and have good knowledge of LabVIEW FPGA programming.

To use the native FPGA in VeriStand, you need a LabVIEW FPGA bitfile (.lvbitx) and an FPGA configuration file (.fpgaconfig). VeriStand includes bitfiles and FPGA configuration files for many FPGA targets. You can find them at %Public%\Documents\National Instruments\NI VeriStand (Year)\FPGA. If you can't find the hardware you are using there, you must create a custom bitfile and FPGA configuration file. 

LabVIEW FPGA bitfile

1. Browse to %Public%\Documents\National Instruments\NI VeriStand 2023\FPGA\Templates.
2. Create a copy of NI VeriStand IO PXI-7854R.lvproj for R Series Multifunction RIO FPGA target or NI VeriStand FPGA IO cRIO.lvproj for CompactRIO FPGA target.
3. Replace the FPGA target with the hardware you are using.

• Remove the FPGA target from the project.
• Right-click My Computer and select New>>Targets and Devices.
• In the Targets and Devices dialog box, select the New target or device.
• Select the device you are using and click OK.
• Under the FPGA Target, add NI VeriStand FPGA DMA IO.vi for R Series Multifunction RIO FPGA target or VeriStand FPGA DMA IO - cRIO.vi for CompactRIO FPGA target, DMA_WRITE FIFO, and DMA_READ FIFO.
• Right-click the FPGA target and select New>>FPGA I/O to add the available I/O resources.

4. Open the FPGA VI in LabVIEW.
5. Update the FPGA VI based on the device and your purpose. The following figure shows that 4 AI channels and 4 AO channels are configured.

            Note: Update the corresponding I/O nodes with the correct pins available on the FPGA target.

6. After updating the FPGA VI, compile the VI into a bitfile.

FPGA Configuration File

1. Download the source code of VeriStand FPGA Configuration Editor from Github.
2. Open the VeriStand FPGA Configuration Editor.lvproj LabVIEW project and build the VCE build specification.
3. After the build, the editor is located at \Tool_Veristand-FPGA-Configuration-Editor-vCE--master\Export\2014\EXE.
4. Run the executable VCE.exe to open the editor.
5. Open an FPGA configuration file located at %Public%\Documents\National Instruments\NI VeriStand (Year)\FPGA as the baseline, then update it according to the LabVIEW FPGA VI. The following figure shows that 4 AI channels and 4 AO channels are configured that align with the above LabVIEW FPGA VI.

6. Click Save, then Exit.
7. Copy the custom bitfile and configuration file to %Public%\Documents\National Instruments\NI VeriStand (Year)\FPGA, then you can add your hardware under the native FPGA in VeriStand.