How to achieve different sampling rates on each RF channel of an X410?

Issue Details

I know that the 4 RF channels on a USRP X410 could work independently for sure.
Now I'm wondering how to actually code it to achieve having different sampling rate on each RF channel of an X410 like the table we listed for N310:


How do we actually implement this (in terms of UHD code) on a X410?

Solution

Let me try to list some mandatory checkpoints as below:

1. FPGA image: has to be flashed to X4_200 or UC_200 (as CG _400 is operating at full-rate, don't use CG _400)

2. Specify the master clock rate to 245.76e6:

   // Assumption: We are using a USRP X410, with a 200 MHz FPGA image
   auto usrp = uhd::usrp::multi_usrp::make("type=x4xx,master_clock_rate=245e6");
   // 245 MHz is not a valid master clock rate!
   std::cout << usrp->get_master_clock_rate() << std::endl; // Prints 245.76e6
   // Changing the master clock rate is not allowed:
   std::cout << usrp->set_master_clock_rate(250e6) << std::endl; // Prints 245.76e6 and a warning
   // The range is now also fixed:
   std::cout << usrp->get_master_clock_rate_range().start() << std::endl; // Prints 245.76e6
   std::cout << usrp->get_master_clock_rate_range().stop() << std::endl; // Prints 245.76e6
   

3. Invoke the APIs below

   uhd::usrp::multi_usrp::set_rx_rate and 
   uhd::usrp::multi_usrp::set_tx_rate

   to set the sample rate directly for each RF channel
   
   That should do the trick and use the DDC/DUC in the fpga to set the IQ data rate. The ADC/DAC rate and radio block master clock rate will remain constant for all channels.
    You may also look at any of our examples to get additional programming insides - github.com/EttusResearch/uhd/tree/master/host/examples