Why Aurora 8b1b0 with Framing From Community Project Does not compile

Updated Dec 1, 2023

Issue Details

I need to change the IP configuration of the Aurora 8b10b to implement inside a PXIe-6592R board. I am starting from this community example and following the indication provided in the Aurora_8b10b_4x1_NI_6592R.vhd. Nevertheless trying the compile the LabVIEW FPGA Top Level vi, Vivado complains with the following message:

ERROR: [Place 30-640] Place Check : This design requires more GTXE2_COMMON cells than are available in the target device. This design requires 6 of such cell types but only 4 compatible sites are available in the target device

Solution

The Aurora8b10b IP provided by Vivado instantiaates some primitives such as GTXE2_COMMON. On this FPGA (xc7k410tffg900-2), there are limited number of these primitives and this message indicates the limit has been exceeded. In fact, on the community example, there are some steps to remove the use of GTXE2_COMMOM by editing the aurora_8b10b_0_support.vhd file.

Before configuring the IP from the Wizard, make sure Vivado is not using the caching files of the IP. This option is by default activated to reduce compilation time. In that way the modification done in the aurora_8b10b_0_support.vhd are not considered.

To apply this change, go to Tools --> Settings -->IP Cache.
The button "Clear Cache" clear the current cached IP, while the "Cache scope" set to "Disable" apply for permanently.

IP Cache settings