Refer to the LabVIEW High performance FPGA Developer's Guide
for optimization techniques and best practices for Hight throughput FPGA applications. The DRAM buffer implemented in this guide can effectively help in handling the transient issues described in the Data Transfer Mechanisms chapter from page 73. However since DRAM has very high possible Data Rate (800MB/s - 10.5 GB/s
) you can easily run into situations where you exceed the PCIe lane bandwidth. The aforementioned chapter from the book also contains guidance on how to avoid these situations.