How-to Implement DRAM Buffer for Data Acquisition in LabVIEW FPGA

Read the following guide first to understand the basic principles of DRAM
Create your project and add your FPGA target and adapter module if you have one
Create your required ADC Clock, for the example 5734 and 7965R this will be a 120 MHz Base Clock using IO Module Clock 0
Create a single cycle timed loop clocked by the ADC Clock
Put your I/O nodes, a Fetch Length (U32) and a Software Trigger (BOOL) Control into the loop

Check the datasheet of your I/O module for the resolution and voltage range of your ADC-s. The 5734 has 16 bit ADC-s on each channel and +-10V of voltage range.
Create an indicator for a channel on your I/O node and check the data type. The 5734 is returning U16 data as it can be seen on the above screenshot. In this case it’s recommended to convert the U16 input to I16 using XOR gates and inserting a binary formatted U16 constant (right click on the U16 numeric constant >> Display Format >> Select binary) where the first number is one and the rest 15 digits are 0. The principle is based on Two’s complement, this logical operation will transform the range of measurement values from [ 0 … 65535 ] to [-32768 …. +32767] in order to better represent the +-10V input range

Read this guide carefully to understand why the appropriate access size and optimal clock rate is very important in the case of DRAM. Find your device in the provided Table. No matter what device you use, you should always try to use it’s DRAM with these parameters if possible. The 7965R has

Currently we have

Therefore we need to

Create a custom control of a cluster equal to the access size of your DRAM, in our example this will be two U64-s. Name the members Upper and Lower. This will be used to maximize all 128 bits of the DRAM interface.
Create a target-scoped DMA FIFO from block memory. It will transfer data to another clock domain for writing to DRAM. Change the data type of the FIFO to use the custom control

You can use the Join Numbers node for bit packing to your access size. In the case of 7965R and 5734 it will take two iterations worth of data (2 iterations x 4 x 16 bit) to fill the 128bit FIFO created in Step 9. So you will only write to it every other clock cycle after the trigger condition. Use a Feedback Node to retain the prior iteration’s ADC data and put it in the Lower member of the 128-bit cluster. Put the current iteration’s ADC data in the Upper member.

You will also need to control on which cycles the FIFO write is enabled. On the first cycle that the trigger is received, you should not write to the FIFO because you only have 64bits of acquired data since the trigger. You should rather write in the following cycle and every other after until the Fetch Length is reached. Be sure to properly implement an appropriate counter with the initial conditions to provide this behavior too besides counting the iterations for the Fetch Length. Here is one possible implementation:

Create a clock equal to the optimal rate of the DRAM on your device. In the case of our example setup it will be a base clock based on the the default 100 MHz clock
Create a single-cycle timed loop using this clock

Add a new memory named ,,DRAM 0” to your FPGA target in the Project Explorer with the 128-bit custom cluster data type, configure it to the size needed in your application.

Build code to read the ADC FIFO and write to sequential addresses in DRAM. You will have to build a counter to do this, reading /writing only by counting when new, valid data is available. Here is one possible implementation:

Create a DMA Target to host FIFO for transferring data to the host. Since the maximum size for this FIFO is a U64, use that, but we will have to de-interleave the data in a subsequent step.
Since we are assuming that the host will not request data from DRAM until the acquisition completes, we do not have to implement DRAM arbitration. But we must signal when this acquisition completes. See the Acquiring indicator in the ADC loop for this purpose at Step 13.
There are 4 conditions which must be met before we can request data from DRAM for transfer to the host:

Acquiring must be false
There must be room in the DMA to host FIFO to receive the data returning from DRAM. To be safe, this should be larger than the size of the “Maximum outstanding requests for data.”
The DRAM Request data node must be ready for input
We must not attempt to read from an address which has not yet been written to

The following code is one such way of implementing this:

Add the Target to Host DMA FIFO configured with U64 to the block diagram
The DRAM Retrieve Data node can be executed on every clock cycle, except for those immediately following a successful retrieval. This is due to the fact that the DRAM will return 128 bits, and it will take two 64-bit writes into the DMA to Host FIFO to successfully return the data. Delay the MSBs until the second write to return the ADC data in-order. “Stretch” the output valid pulse from the DRAM Retrieve Data to write to the DMA to Host FIFO twice. Ensure that you do not retrieve data on the subsequent clock cycle. Here is one possible implementation:

Build your Host VI using FPGA best practices. Note that the conversion with the ,,to I16” node happens on the Host after the split number nodes. It’s important that this step should not replace rather follow the XOR logical operation on the FPGA described at step 7.

Environment