How to Synchronize PXIe-517xs When Using FPGA IDLs

Updated Jul 7, 2021

Environment

Hardware

  • PXIe-5170
  • PXIe-5171
  • PXIe-5172
  • PXIe-6674T

Software

  • LabVIEW
  • LabVIEW FPGA Module

Driver

  • LabVIEW Instrument Design Libraries for Reconfigurable Oscilloscopes
  • NI-Sync

Overview

When using multiple PXIe-517x NI Reconfigurable Oscilloscope cards and there is a need to synchronize them, than there are two options for the user:
  1. Using the NI-SCOPE Driver with NI-TClk for synchronization implementation - NI-SCOPE Examples
  2. Using the LabVIEW Instrument Design Libraries for Reconfigurable Oscilloscopes and generic PXIe trigger and clock sharing

In this article we are exploring the second option and it's technical background. For the code which implements the theory, what this article lays out, please refer to the links in the Example section.

 

Implementation

This implementation leverages two components of the basic synchronization scheme:
  1. Common Start Trigger
  2. Shared Synchronization Clock
 

Common Start Trigger

Sharing a common digital pulse(Start Trigger) between instruments can help start the acquisitions at the same time. In our case we use the PXIe-DStarB lines to share the Start Trigger on the PXIe backplane.


PXIe DStarB on 5171 block diagram
Figure 1. PXIe_DStarB on PXIe-5170/5171 Block Diagram

 
If we have access to the PXIe-DStarB dedicated trigger lines in the PXIe chassis we can send Start Triggers always on the same length of route. The PXIe-517x cards have connections to the PXIe-DStarB and C lines. We are only interested in the B lines since they are the ones where triggers arrive and C lines are responsible trigger sending. ​​​The PXIe_DStarB lines connect the system timing module to each peripheral slot in a PXI Express chassis, allowing the system timing module to send out high speed triggers to every slot.  PXIe_DStarB uses differential LVDS signaling and closely matched trace lengths to achieve faster, more precise triggering than is achievable with PXI_STAR or PXI_TRIG.

In our examples we are using the PXIe-6674T PXI Timing Module which is capable of sending a Global Software Trigger to trigger the acquisitions of the PXIe-5171s.

 

Shared Synchronization Clock

Having only a common Start Trigger is not enough to keep our measurements in sync throughout the entire acquisition. This is because all of our instruments generate their own clock signals onboard. To avoid the instruments getting desynced a common clock signal has to be shared amongst the instrument to use as a clock signal or to phase lock the onboard signal.
In our example we are using the PXIe-6674T's very accurate temperature controlled OCXO 10MHz clock signal to replace the PXIe chassis voltage controlled VCXO 10MHz backplane clock and use it as a Reference Clock for all the PXIe-5171 in the system.


ocxo.png
Figure 4. PXIe-6674T Functional Overview of OCXO

 
The PXIe-6674T features a precision 10 MHz Oven Controlled Crystal Oscillator (OCXO). The main source of frequency error in reference oscillators is temperature variation. An OCXO minimizes this error by housing the crystal oscillator circuit inside a sealed oven, which is maintained at a constant temperature higher than the ambient temperature external to the OCXO. This results in a reference oscillator that is several orders of magnitude more stable and accurate than regular crystal oscillators.

As seen in Figure 4 he PXI_CLK10_IN is a signal that can be used to provide the backplane with a reference 10 MHz signal from the system timing slot. When a 10 MHz signal is connected to PXI_CLK10_IN, the PXI Express chassis is required to derive PXI_CLK10 and PXIe_CLK100 from this reference.

Result

fp.png
 

Example

example.png