Synchronizing NI Linux RT PXIe to cRIO Using Time-Sensitive Networking

For Condition Monitoring Applications for Aerospace Boards, NI recommends NI PXI Express & CompactRIO Real-Time Systems, which provides high-performance, high channel modular instruments, Time Sensitive Networking (TSN) enabled synchronization. TSN technology or IEEE 802.1AS which is an update to the IEEE Ethernet provides Standard Time Synchronization & Deterministic Network Communication. NI offers a wide variety of cRIO, cDAQ & FiedDAQ products that are used to build high-quality distributed TSN Ethernet-based measurement systems. However, the capability of using TSN technology is still evolving for NI Linux Real-Time PXIe controllers.

This article will guide through the configuration steps for synchronizing NI Linux Real-Time PXIe System as Master using PXI Synchronization Module 6683(H) with multiple TSN enabled slave NI cRIOs connected using NI cRIO 9805 TSN Switch.

To use the time-based synchronization and TSN feature, install NI Sync 19.0. The support for TSN or IEEE 802.1AS is added in NI-Sync 19.0 for Linux RT. The article assumes the reader is familiar with working on NI LabVIEW and PXIe Controllers with NI Linux RT OS.

To configure and verify the TSN Synchronization, this article focuses on

• PXIe System with PXI 6289 PXI Multifunction I/O Module  - used for LoopBack Configuration.
• PXI 6683H - used as the Timing and Synchronization Module.
• cRIO 9085 Switch - used as TSN Network Switch.

Hardware Configuration

1. Ensure the PXI-6683(H) is placed in the Hybrid Slot of the PXIe Chassis.

2. Ensure the external connection from CLK OUT on the PXI-6683(H) is connected to 10MHz REF IN on the back of the PXIe chassis. This is required to drive the chassis' reference clock.

3. Complete the below connections for testing synchronization, loopback & trigger:
   1. Synchronization Connections:
      1. cRIO 9805 Switch Port 1 to 6683H Ethernet Adapter
      2. cRIO 9805 Switch Port 2 to cRIO 9047 Ethernet Port
      3. cRIO 9805 Switch Port 3 to cRIO 9057 Ethernet Port
   2. LoopBack Connections:
      1. cRIO 9047 NI 9263 AO 0 to cRIO 9047 NI 9232 AI 1
      2. cRIO 9047 NI 9263 AO 0 to cRIO 9057 NI 9232 AI 1
      3. cRIO 9047 NI 9263 AO 0 to PXI 6289 NI 9232 AI 15
   3. Trigger Connections:
      1. PXI 6289 PFI 0 to cRIO 9047 PFI 0
      2. PXI 6289 PFI 0 to cRIO 9057 PFI 0
      3. PXI 6289 PFI 0 to PXI 6289 PFI 1

Software Configuration

1. Open LabVIEW 2020.
2. Navigate to Help>>Find Examples>>Hardware Input and Output>>Timing and Synchronization>>Time-based>>Set Time Reference.vi.
3. Open the block diagram of Set Time Reference.vi.
4. The dropdowns currently do not include IEEE 802.1AS so modify the polymorphic niSync Set Time Reference.vi to use 802.1AS instance.
5. Set the resource name to PXI 6683H slot to set the 802.1AS time reference for PXIe as master.
6. Save As the Set Time Reference.vi.
7. Navigate to Help>>Find Examples>>Hardware Input and Output>>Timing and Synchronization>>Time-based>>Discipling PXI_Clk10 to Time Reference.vi to discipline the PXI_Clk10 using a single board disciplining capable Timing module. This step is necessary for driving the chassis' reference clock as mentioned in Step 2 of the Hardware Configuration section.

8. Refer to Syncing PXI Cards to TSN Network for more details on configuring the Disciplining PXI_Clk10 to Time Reference.vi.
9. Navigate to Help>>Find Examples>>Hardware Input and Output>>Timing and Synchronization>>Time-based>>Monitor & Configure Time References.vi to monitor 802.1AS Time Reference is running on Real Time System.
10. Set the resource name to PXI 6683H slot and run the VI.
11. Verify the Clock State of PXI 6683H is configured as “Master” with its corresponding Grand Master Clock ID.
12. Modify the resource name to cRIO 9047 and run the VI again.
13. Verify the Clock State of cRIO 9047 is configured as “Slave” with its corresponding Grand Master Clock ID is of PXI 6683H.
14. Modify the resource name to cRIO 9057 and run the VI again.
15. Verify the Clock State of cRIO 9057 is configured as “Slave” with its corresponding Grand Master Clock ID is of PXI 6683H.

After performing these steps, the TSN synchronization is configured for PXI as Master and cRIOs as slaves and is verified by modifying the Time Synchronization example VIs for TSN.
The shipping examples for DAQmx Voltage Analog Input and Analog Output can be deployed to verify the LoopBack connection.

1. PXI,cRIO 9047 & 9057 Data Acquisition VIs are waiting for Trigger to start the acquisition at the same time.
2. Once the trigger is activated using the NI MAX test panel at PFI 0; PXI, cRIO 9047 & 9057 starts acquiring the data.