Inlining VIs Is Not Allowed on FPGA Targets

Updated Jun 6, 2023

Issue Details

I have created some VI for my PC and I might like to compile the code for cRIO FPGA targets in some cases. I found that if you want to compile a VI for an FPGA the option to inline the VI is not available. 

  • Why is this option not allowed? 
  • How does it affect the performance of the VI? 
  • Do I have to create a copy of the VI so I can avoid errors during compilations if the VI for the FPGA is originated from a host VI with Inlining enabled?


When running LabVIEW code on a desktop or real-time system, there is generally some overhead involved in a subVI call as data can be copied before being passed into subVIs. In LabVIEW FPGA, because your LabVIEW diagram is converted to a hardware circuit, you do not have the same overhead of calling subVIs. Since the code is running in hardware, there is no operating system that has to make data copies or load VIs into memory. These overheads are removed by the process of compiling for hardware, the same way that inlining removes them when running code on a computer processor. 

In short, on the FPGA VIs inlining is done automatically when the code is compiled to an FPGA bitfile image. You can have subVIs in your main FPGA VI, but these subVIs will be part of the image when the main VI is compiled, and will be mapped to hardware as part of the main image.

There will be no issues with the compilation if your VI had inlining originally enabled. This option will be simply ignored.