To execute a Single Cycle Timed Loop (SCTL) at a rate other than the default 40Mhz, you first need to create a new FPGA derived clock at your desired rate. FPGA derived clock rates can be specified between 2.5MHz and 210MHz. To create a derived clock, right click the
40MHz Onboard Clock in your project explorer window and select
New FPGA Derived Clock as shown in Figure 1. In the
FPGA Derived Clock Properties window, you can adjust the clock
Multiplier and
Divisor to achieve your desired clock rate as shown in Figure 2. Pay close attention to any comments generated in the
Message field, they will let you know if you have requested a valid configuration.
Figure 1
Figure 2
To force the SCTL to use the new derived clock, right click the left hand timing block of the SCTL and select
Configure Input Node as shown in Figure 3. In the
Configure Timed Loop dialog, select the
Select Timing Source radio button and click your derived clock under
Available Timing Sources and click
OK as shown in Figure 4. Your SCTL will now execute at the frequency of your derived clock.
Figure 3
Figure 4
Note: Some code may not compile at rates above 40MHz, due to timing constraints of the FPGA. The compilation report summary will list an error if your code was not able to be compiled at the derived clock rate.
Additional Information
If none of these rates are suitable for your application, you should review this example program
Configure Sample Rate of Single Cycle Timed Loop in LabVIEW which demonstrates how to configure a custom sample rate of a FPGA Single Cycle Timed Loop.