Synchronizing the R Series or FlexRIO FPGA Clocks to the PXI Backplane

I would like to synchronize the FPGA clock of my R Series or FlexRIO PXI(e) board to the PXI(e) 10 MHz or 100 MHz backplane clock. Is this possible, and if so, how do I do this?

It is possible to synchronize the FPGA clock on a PXI(e) R series or FlexRIO device to the 10 MHz or 100 MHz backplane clock. These devices contain a Phase-lock Loop (PLL) that allows the FPGA clock to synchronize to the PXI(e) clock. Depending on which device you are using, the process is different. 

 

FlexRIO

The FPGA clock on a FlexRIO device is always synchronized to the 10 MHz or 100 MHz clock on the PXI(e) chassis. In particular, PXIe FlexRIO cards synchronize to the 100 MHz clock, and PXI FlexRIO cards synchronize to the 10 MHz clock.

R Series

The FPGA clock on PXIe R Series Devices is always synchronized to the 100 MHz clock when using the R Series Driver before version 15.0. As of version 15.0.0 of the driver, the FPGA clock is not synchronized to the PXIe_CLK100 and may drift overtime. To fix this issue, install the NI R Series Multifunction RIO Device Drivers version 19.0 or later. The Q1 2019 patch specifically resolved the issue.

By default, PXI R Series boards are not synchronized to the PXI backplane clock. You must manually enable this feature from within LabVIEW.  Once this setting has been enabled, it will remain stored on the board until it is manually changed again. This setting will persist even if the board is powered down or moved to a different chassis.

​To enable synchronization in LabVIEW 8.5 and above: 

1. Right-click the FPGA target and select RIO Device Setup...
2. In the RIO Device Setup window, select the Device Settings tab
3. Enable the check box marked Synchronize FPGA Clock to PXI_CLK10
4. Press the Apply Settings button to download the settings to the R-Series card
5. Power cycle the board (restart the PXI chassis) or recompile the bitfile for the change to take effect

To enable synchronization in LabVIEW 8.2.1 and below:

1. Right-click the FPGA target and select Download Bitfile or Attributes To Flash Memory...
2. In the Download Attributes or Bitfile to Flash Memory window, enable the check box marked Synchronize FPGA Clock to PXI_CLK10
3. Press the Download Attributes button to download the settings to the R Series card
4. Power cycle the board (restart the PXI chassis) for the change to take effect

Additional Information

PXI chassis only have a 10 MHz clock while PXIe chassis have a 10 MHz and 100 MHz clock.

The PXIe 10 MHz clock and 100 MHz clock have a fixed phase relationship as described in the PXIe chassis user manual. Thus, a PLL of the FPGA clock to the one backplane clock automatically creates a fixed phase relationship to the other clock.

PXI Clock 10 could be used as a base level clock with the PXIe R Series. This is synonymous to deriving a 10 MHz clock from the 40 MHz on-board oscillator.