You can use Multisim to create specialized schematics that describe the logic of a PLD, such as the FPGA on the NI Digital Electronics FPGA Board (DEFB). Multisim also includes configurations to automate creating synthesizable and implementable designs for the DEFB.
Figure 1. NI Educational Laboratory Virtual Instrumentation Suite (NI ELVIS) II+ and the NI Digital Electronics FPGA Board Top
This article describes the step-by-step process, from DEFB creation to programming, using Multisim and Xilinx ISE Tools. As a test design, you can implement simple OR logic using two switches and one LED on the DEFB. Again, you can use a similar process to program other FPGAs.Follow these three steps:
Note: You may use earlier versions of Multisim with earlier versions of Xilinx ISE Tools. Verify the version compatibility in the release notes for earlier releases of Multisim.
The first step is to create a new PLD design in Multisim. In this example, use the standard configuration for the DEFB. This configuration file is configured to automatically map Multisim signals to the appropriate pins on the FPGA.
The next step is to describe the logic for the OR gate.
Figure 2. Multisim PLD Design Snippet: Drag and drop into Multisim 12.0 or later to import logic.
To export the digital logic, navigate to Transfer»Export to PLD...You can choose from three options to export the PLD logic: (1) program the connected PLD with the option to save the programming file (if the PLD is connected and detected), (2) generate and save the programming file, and (3) generate and save VHDL files. All three have unique benefits, which are explained further in the next three sections.
The benefit to programming the connected PLD is that it allows you to validate the digital logic with hardware, providing immediate results. The drawback is that you must connect the hardware to the computer for programming.The following procedure outlines how to program a connected DEFB.
If hardware is not immediately available and the end goal is to deploy to an FPGA, you can generate and save a programming file targeted for an FPGA. This file is the closest step to actually programming the physical FPGA, allowing a student to bring the programming file to class and quickly deploy to the FPGA to get results using the Xilinx ISE Tools. The following procedure outlines how to generate a programming file using a Multisim PLD export:
At the culmination of most introductory digital logic courses, students are introduced to hardware description languages (HDLs). A powerful feature of the PLD schematic is the ability to generate VHDL code from the PLD logic in Multisim. Using Xilinx ISE Tools, students dive deep into VHDL and add critical timing constraints to the generated VHDL code when required. The following procedure outlines how to export the digital logic to VHDL in Multisim.
1. Select Generate and save VHDL files as shown in the image below. Select Next to proceed.
2. Select the name of the Top level module file. You may also specify if you prefer to Customize package file name. If you do not specify this, Multisim appends _pkg to the end of the specified top level module name. Select Finish to generate the files.
3. You can now open and explore the resulting VHDL files as well as import them into Xilinx ISE Tools to add timing constraints.
Multisim continues to provide a best-in-class teaching solution for circuit theory, including Digital Logic, with the continued support for Xilinx FPGA tools. The PLD schematic offers a graphical environment to better understand the fundamentals of digital gates, and then smoothly transition to more advanced concepts such as combinatory logic, and finally, students can explore VHDL and program PLDs.
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