View the complete Teaching Digital Logic Fundamentals tutorial series
When moving beyond simple logic diagrams, timing soon becomes a critical part of digital design. Gaining a comprehension of timing is difficult without using hardware because of the inability for software based simulations to meet the speed of those running in hardware.
Typically, using traditional approaches this would require the student to learn advance Hardware Descriptive Languages such as VHDL and Verilog. Using Multisim and the PLD schematic students can gain experience of using counters in hardware before the need to learn these more advanced descriptive languages. This tutorial is going to provide an example of how students can develop counters using Digilent boards and use these to control the onboard 7 segment displays.
Whilst this tutorial and the accompanying example were produced using the Digilent Nexys 3 the same could be achieved on other Digilent boards. More details on installing and targeting a range of Digilent boards from Multisim can be found here:
Getting Started with Digilent Boards in Multisim.
This tutorial will be broken down into three sections. Firstly we will discuss the top level schematic which is used for simulation purposes and contains the PLD subsheet. The next section will explain the PLD schematic and its various components. The final section will talk through running the logic both as a software simulation and on Digilent education boards.
The top level schematic, as part of this project, allows for simulation. It places the PLD logic in place around the IO contained on the board. To achieve this we use a PLD sub-circuit. The PLD sub-circuit allows us to place the PLD code within a single component as if it was being run on the FPGA.
The steps below describe the process for creating a sub-circuit.
CLK – 50MHz clock on the board
BTNU – Push button located on the board to reset the counter
an_0:3 – 4 Digital lines to control which of the four 7 segment displays to display
seg_0:6 – 7 Digital lines to control what each of the 7 segment displays displays
After completing the top level circuit we need to create the digital logic within the PLD schematic. In this example we are creating a simple up-counter and the required logic to control the four 7 segment displays. The PLD code needs to have two main functions:
To create the PLD schematic double click the PLD sub-circuit and select Open subsheet from the properties window.
The figure below shows the three main sections of the PLD schematic. The main counter provides a clock signal to both the update counter and the display counter. The update counter controls which of the four displays needs updating. The display counter determines the value to be updated on that counter.
Each of the four display counter blocks contain a subsheet containing:
The above PLD code can be simulated through running the top level circuit and viewing the display on the virtual 7 segment displays. During execution the seven segment displays are illuminated one at a time to display the count.
Within the simulated PLD code a shift register in the update counter section controls which of the seven segment displays is updated. This is then passed out of the PLD schematic and the transistors regulate which of the displays gets illuminated. The virtual BTNU button can be triggered to reset the counter.
The next stage of learning about the behavior of the circuit is to deploy the code to the Digilent board. This can be done by opening up the PLD subsheet and transferring to PLD as described in:
Getting Started with Digilent Boards in Multisim
The components featured on the top level schematic will now be replaced with the physical components on the board.
When deploying the PLD schematics featured above the student will notice that the seven segment LEDs appear illuminated constantly and it is not possible to view the count. This illustrates the FPGA on the Digilent board being able to run much faster than the software on the PC. This is the same with any software simulation of FPGAs and an important lesion which the students can learn first hand.
To overcome this we can step down the 50MHz clock further so that it is slow enough to allow us to view changes increments. This can be seen below with the addition of 5 counters 4-bit counters.
Once we deploy this logic we will see the 4 seven segment displays illuminated and performing the count operation.
All the files for this tutorial can be found in the attached file. This tutorial provides an example of how students can learn the fundamental theory behind digital logic counters and deploy these to hardware before the need to learn advanced Hardware Description Languages such as VHDL.
Download the tutorial files here.
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