The top level schematic, as part of this project, allows for simulation. It places the PLD logic in place around the IO contained on the board. To achieve this we use a PLD sub-circuit. The PLD sub-circuit allows us to place the PLD code within a single component as if it was being run on the FPGA.
The steps below describe the process for creating a sub-circuit.
- Open a new schematic.
- Select Place » New PLD sub-circuit
- Select the Digilent board you will be using from the drop down menu.
- Provide a name for the PLD schematic.
- Select the connectors that you will be using on the PLC. For the counter in this tutorial we will be using:
CLK – 50MHz clock on the board
BTNU – Push button located on the board to reset the counter
an_0:3 – 4 Digital lines to control which of the four 7 segment displays to display
seg_0:6 – 7 Digital lines to control what each of the 7 segment displays displays
- This will then generate the PLD block and you can place it on your schematic. This represents the FPGA on the Digilent board providing access to the various IO.
- The symbol can be modified from the shortcut menu by selecting Edit symbol/title block.
- This opens the Symbol Editor that can be seen below where we can create a custom symbol and rearrange the terminals.
- Save the symbol when complete and return to the schematic. From here we can create the components that feature on the Digilent board allowing us to simulate the schematic. The annotated figure below shows the required components for the simulation.
After completing the top level circuit we need to create the digital logic within the PLD schematic. In this example we are creating a simple up-counter and the required logic to control the four 7 segment displays. The PLD code needs to have two main functions:
- Control the illumination of the seven segment display
- Perform the up-counter operation.
To create the PLD schematic double click the PLD sub-circuit and select Open subsheet from the properties window.
The figure below shows the three main sections of the PLD schematic. The main counter provides a clock signal to both the update counter and the display counter. The update counter controls which of the four displays needs updating. The display counter determines the value to be updated on that counter.
Each of the four display counter blocks contain a subsheet containing:
- Individual counter that calculates the value for that display before passing that value onto the next display counter block.
- A 7 segment-decoder to take the counter value and output the required states on to the 7 segment display.
- A buffer for each of the seven lines leading to the display.
Simulating and Deploying Logic
The above PLD code can be simulated through running the top level circuit and viewing the display on the virtual 7 segment displays. During execution the seven segment displays are illuminated one at a time to display the count.
Within the simulated PLD code a shift register in the update counter section controls which of the seven segment displays is updated. This is then passed out of the PLD schematic and the transistors regulate which of the displays gets illuminated. The virtual BTNU button can be triggered to reset the counter.
The next stage of learning about the behavior of the circuit is to deploy the code to the Digilent board. This can be done by opening up the PLD subsheet and transferring to PLD as described in: Getting Started with Digilent Boards in Multisim.
The components featured on the top level schematic will now be replaced with the physical components on the board.
When deploying the PLD schematics featured above the student will notice that the seven segment LEDs appear illuminated constantly and it is not possible to view the count. This illustrates the FPGA on the Digilent board being able to run much faster than the software on the PC. This is the same with any software simulation of FPGAs and an important lesion which the students can learn first hand.
To overcome this we can step down the 50MHz clock further so that it is slow enough to allow us to view changes increments. This can be seen below with the addition of 5 counters 4-bit counters.
Once we deploy this logic we will see the 4 seven segment displays illuminated and performing the count operation.
All the files for this tutorial can be found in the attached file. This tutorial provides an example of how students can learn the fundamental theory behind digital logic counters and deploy these to hardware before the need to learn advanced Hardware Description Languages such as VHDL.
Download the tutorial files from the Attachments section of this article.