Multisim 14.0.1 Education and later comes with built-in PLD support for the NI Digital System Development Board (DSDB) and many other Digilent Boards. This support includes a PLD configuration file that defines the names and properties of port connectors that a Multisim PLD design will use. In addition, a constraint file (UCF in Xilinx ISE and XDC in Vivado) is used to map signals to the FPGA's pins.
To program the FPGA boards, the Digilent driver and Xilinx software and must be installed on your computer which could be Xilinx ISE or Vivado depending on which board you have.
For LabVIEW FPGA users with the LabVIEW Xilinx software already installed, you only have to install the additional Digilent driver. Refer below to see which software you need to install for your board:
NI LabVIEW FPGA Xilinx ISE 14.7 Tools/Digilent Drivers
- Digilent Cmod S6
- Digilent Nexys 2 FPGA Board
- Digilent Nexys 3 FPGA Board
- Digilent Nexys 4 FPGA Baord
- Digilent Basys FPGA Board
- Digilent Basys 2 FPGA Board
- NI Digital Electronics FPGA Board
NI LabVIEW FPGA Vivado 2014.4
- NI Digital Systems Development Board
- Digilent Basys 3 Board
- Digilent CMOD A7
- Digilent Arty
Please only download the FPGA tools that apply to the FPGA board that is being programmed in Multisim.
To install Xilinx ISE, navigate to the tool linked above and go through the typical installation process.
Xilinx Vivado no longer automatically installs the Digilent Driver so to enable support for your Digilent board, the drivers must be installed as well. First, make sure to install the LabVIEW FPGA Vivado tool listed above. Once installed, navigate to C:\NIFPGA\programs\Vivado2014_4\data\xicom\cable_drivers\nt64\digilent and install the install_digilent.exe file to install the Digilent specific drivers.
After any installation, make sure to restart the computer.
Setting up the Multisim PLD Design
Once you have installed the required software and driver, you are ready to program the FPGA board. The steps below describe the process for creating a PLD design for the DSDB FPGA board, the same steps can be used for the other boards.
In Multisim, select File»New.
Click the PLD Design… the click the Create button.
Click the Use standard configuration down arrow and select your board. Click Next.
Enter Introduction to Digital Electronics in the PLD design name field and click Next.
The New PLD Design dialog allows you to select which peripherals you will use in your design. In this tutorial the LED LED0 and the push button BTN0 are selected. Click Finish.
- The selected connectors are placed on the workspace.
Create a PLD Schematic in Multisim
Select a AND2 gate located in the PLD Logic group, Logic_gates family and click the OK button.
- Place another connector for the AND gate input by click the Input connector icon on the toolbar.
- Select the push button BTN1 and click OK.
Wire the AND gate to the connectors.
Export the PLDS Design to the FPGA
There are three options for exporting the digital logic from the PLD schematic:
Programming the connected PLD – Allows students to deploy the design directly to the FPGA.
Generate and save a programming file- Students can generate a bit file that can be used to program hardware later.
Generate and save the VHDL- This option exports the VHDL netlist allowing students to view the VHDL code. You can import the VHDL code in the Xilinx environment and program the FPGA
In this tutorial you will program the FPGA board directly from the Multisim environment.
Select Transfer»Export to PLD.
Click the Program the connected PLD radio button and click Next.
- In the Select a tool to use area, select the Xilinx tool for you board.
Connect the hardware to to your computer and wait for Windows to detect the connection.
Make sure power is applied to the board and the power switch is set to the on position.
Click the Refresh button. The Detected message will appear if the board is detected by your computer.
Click the Finish button to begin programming the board.
Note: Some Vivado versions do not support file path containing spaces for the XDC file. In these cases, you will get an “illegal file or directory name” error when trying to export the design. If this happens, copy the DSDB.xdc file stored in the installation folder:
<Program Files>\National Instruments\Circuit Design Suite 14.0\pldconfig
to a local path such as C:\temp. Next, change the Xilinx user constraint file (*.xdc) in the Multisim PLD Export step 2 of 2 dialog to where you saved the file before exporting the design.
Multisim will automatically open the Xilinx tool in the background and perform all the requires steps to program the FPGA, no user interacting is required.
- Once the FPGA is programmed, Multisim will display a message on the Spreadsheet View.
- You can now test the design built in Multisim on the real-hardware.
The Teaching Digital Logic Fundamentals tutorial series contains a set of examples that can be used with any of the FPGA cards.