Before starting this tutorial, NI recommends reviewing the information in MATLAB, Simulink, and LabVIEW FPGA: Importing HDL Coder into LabVIEW FPGA Designs.
Note: This tutorial assumes familiarity with MATLAB and focuses on the workflow within LabVIEW. For more information and examples of MATLAB, refer to the official documentation and the MathWorks website.
Install the following software with the specified version. Other versions may also work but the UI might be different.
a. The valid_out signal should update at the same point that y_out becomes a valid value. Since the function and test bench assume that y_out is valid after any call of the function, no persistent variable is needed.
b. The x_valid_out signal should receive the same amount of delay as the delayed_xout variable. To accomplish this, add another chain of delay registers:
With the modified function and test bench, you can now create the HDL Coder export, which involves creating an HDL Coder project, determining a fixed-point representation for the function, then configuring the HDL generation parameters.
a. On the Target tab, set the Language to VHDL. LabVIEW FPGA cannot import Verilog without first creating a netlist.b. On the Clocks & Ports tab, ensure that the Clock edge is set to Rising, the Input data type is set to std_logic_vector, and that the Scalarize vector ports option is selected. LabVIEW supports only top-level ports of std_logic and std_logic_vector data types and does not support arrays.c. On the Optimizations tab check both Register inputs and register outputs to ensure that inputs and outputs are registered, which helps designs to integrate more easily when you pipeline the design.
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