Set the PXIe-659xR's Clock to Export

Updated Jul 20, 2023



  • PXIe-6591
  • PXIe-6592


  • LabVIEW FPGA Module

The PXIe-6591R has one SMA connector for clock input and output, and the PXIe-6592R has PFI0/CLK IN for input/output and PFI1, PFI2, PFI3 SMB connectors for output.

  1. Create or open the PXIe-659xR sample project.                                 
  2. In the project explorer, right-click IO Socket under My Computer>> FPGA Target and select Properties.                                                 
  3. Select Clocking and IO and click the checkbox of the connector that will output the clock in Output Clock Configuration.
    • (PXIe-6591R only) When CLK IN/OUT is enabled as an output reference clock, it routes the specified frequency to the SMA connector.
  • (PXIe-6592R only) When PFI 0/CLK OUT, PFI 1, PFI 2, and PFI 3 are enabled as output reference clocks, they route the specified frequency to the corresponding SMB connector.
  • If you specify an invalid combination of input clock frequencies and output clock frequencies, an error message appears and the OK button is dimmed until you reconfigure the clocks to a valid frequency combination. 
  • PXIe-6592R's output clocks only allow simple integer division relationships.
      4. Click OK to complete the setup and save the project.
      5. Compile the FPGA and run it with the host.