Taking a hands-on approach to learning digital logic can be difficult without the need for students to learn complex hardware descriptive languages. Multisim’s Programmable Logic Device (PLD) schematic, along with support for leading Digilent teaching hardware allows students to put the fundamentals of digital theory into practice. The PLD schematic allows educators and students to create graphical logic diagrams like those found in textbooks and deploy these to educational FPGA boards such as the Digital System Development Board (DSDB).
Timing is a critical part of digital design. Because of the inability of software-based simulations to meet the speed of hardware, gaining an understanding of timing can be difficult.
This tutorial provides an example of how you can develop counters using the DSDB or any other Digilent FPGA board and use these to control the onboard 7-segment displays using Multisim and the PLD schematic.
For more details on installing and setting up the DSDB in Multisim, refer to the Getting Started with Digilent Boards in Multisim guide.
You will need the following for this tutorial:
Refer to Multisim Won't Recognize My Digilent FPGA Board for more information.
The top level schematic, as part of this project, allows for simulation. It places the PLD logic in place around the IO contained on the board. To achieve this we use a PLD sub-circuit. The PLD sub-circuit allows us to place the PLD code within a single component as if it was being run on the FPGA.
The changes are reflected on the schematic.
This section details how to create the digital logic within the PLD schematic.
In this example we are creating a simple up-counter and the required logic to control the four 7-segment displays. The PLD code must control the illumination of the 7-segment displays and perform the up-counter operation.
Note: You can skip this step and use the completed files that are referenced at the end of this document for the remainder of this tutorial, but it is recommended that you read the descriptions of the PLD subcircuit functionality below.
The figures below show the three main sections of the PLD schematic.The Main Counter provides a clock signal to both the update counter and the display counter:The Update Counter selects the 7-segment display to be updated:The Display Counter determines the value to be updated on the selected 7-segment display:
Each of the four display counter blocks are represented by a subsheet containing:
The above PLD code can be simulated by running the top level circuit and viewing the display on the virtual 7-segment displays. During simulation, the displays are illuminated one at a time to show the count.
Within the simulated PLD code a shift register in the update counter section controls which of the7-segment displays is updated. This is then passed out of the PLD schematic and the transistors regulate which of the displays gets illuminated. The virtual BTN0 button can be triggered to reset the counter using the space bar.
In this step, you will deploy the PLD code to the DSDB board, where the components on the top-level schematic are replaced with physical components.
Because the hardware operates much quicker than the simulation, some modifications must be made to make the 7-segment displays on the DSDB readable, as opposed to appearing constantly lit. This can be done by adding additional counters to step-down the clock frequency, as shown below:
Rather than modifying your existing simulation schematic, you can open DSDB for board.ms14, and export its contents to the DSDB. This file contains only the components from the PLD subcircuit in DSDB for simulation.ms14.
The PLD logic is exported to the DSDB. This may take several minutes. When complete, the7-segment displays will start counting.
To reset the count, press switch BTN0.
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