There are two main aspects that can be used to distinguish between previous generation R Series and newer generation R Series:
For more details on each R Series model you can go to the following link and consult the table 1. NI R Series Multifunction RIO Frequently Asked Questions (FAQ)
By default, FPGA I/O Nodes for analog input and output channels on USB/PXIe/PCIe R Series devices use the fixed-point data type, which provides data in calibrated engineering units. For FPGA applications, the fixed-point data type is advantageous over floating point because it can be processed much faster and can significantly reduce the number of resources you use on the FPGA. For a more detailed discussion on the fixed-point data type, see LabVIEW FPGA Floating-Point Data Type Support. NI recommends using the fixed-point data type for most FPGA applications.
There are, however, cases where using raw data over calibrated data is advantageous such as when streaming data to achieve the maximum acquisition rate (1 MS/sec) on all AI channels simultaneously. Additionally, raw data uses the I16 data type, which allows you to join it with a other I16's to create a single I32 or I64 that can be placed in a single DMA FIFO element for the most efficient transfer to the host. Another case where raw data is advantageous is when FPGA resources are limited and the additional processing required for fixed-point data exhausts all the available FPGA resources.
Once you’ve identified calibrated or raw as your preferred data type, you may need to change the I/O configuration. For USB/PXIe/PCIe R Series devices, calibrated is the default so these steps may not be necessary.
From the LabVIEW Project Explorer right-click FPGA Target»Change I/O Configuration… as shown in Figure 1.
Figure 1. Change the R Series I/O configuration from the LabVIEW Project Explorer
Figure 2. Configure R Series I/O
After you have configured the I/O and placed an FPGA I/O Node on the block diagram, the calibrated data node appears as shown in Figure 3.
Figure 3. Appearance of FPGA I/O Node—Calibrated (Fixed-Point) Data Type
An FPGA I/O Node for raw data appears as shown in Figure 4.
Figure 4. Appearance of FPGA I/O Node—Raw (I16) Data Type
LabVIEW FPGA code written for previous generations of R Series devices should run without error on USB/PXIe/PCIe R Series devices. However, after converting binary data to engineering units, you may notice that your current-generation R Series device yields a different result than that obtained by a previous-generation R Series device. This is because of a difference in the way calibration is implemented.
On previous-generation R Series devices, raw data from the analog-to-digital converter (ADC) is calibrated in hardware and passed to LabVIEW where it is read as an I16 with an FPGA I/O Node. This is slightly different for USB/PXIe/PCIe R Series devices where uncalibrated raw data is passed directly to LabVIEW from the ADC. From there, the data then needs to be calibrated in software. This difference in calibration is mostly responsible for inconsistencies you may see between devices.
The device’s operating voltage range also contributes to a difference in measurements obtained from different devices. You can find this range in the applicable R Series Specifications manual. For example, a previous-generation R Series device has a slightly smaller operating voltage range (±10 V) than USB/PXIe/PCIe R Series devices (±10.63 V). This difference changes the weight of each least significant bit (LSB), which prevents a 1-to-1 mapping of binary to nominal values between targets. As such, you must be aware of these subtle differences and account for them when developing code intended for use with multiple R Series devices.
When a USB/PXIe/PCIe R Series analog channel is configured for raw data and read into LabVIEW through an FPGA I/O Node, the resulting binary (I16) data is uncalibrated. You can calibrate this data through the following process, which requires a LabVIEW host VI (Windows or Real Time) and the binary to nominal VI (analog input) or nominal to binary VI (analog output). These VIs are accessible from NI USB/PXIe/PCIe R Series examples.
From your FPGA VI (Figure 5):
From your host VI (Figure 6):
Collaborate with other users in our discussion forums
A valid service agreement may be required, and support options vary by country.