Control a Variable Valve Timing (VVT) System on an Internal Combustion Engine

In modern engines, you must adjust intake and exhaust cam timing in real-time to meet emissions and performance requirements. Several auto equipment manufacturers implement real‐time cam timing adjustment mechanisms, which are often referred to as variable valve timing (VVT). A common implementation involves a mechanical device that allows the camshaft to move through an angular range with respect to the belt‐driven pulley. An oil control valve controls the adjustment hydraulically. The oil control valve is controlled by a pulse‐width modulating electrical current to a solenoid, which modifies the valve orifice. To achieve a desired cam phaser position, you need a position feedback signal. This is typically a digital pulse train generated by a trigger wheel attached to the spinning camshaft. As the oil control valve adjusts the cam phase, the cam phase’s digital pulse train changes its in-phase relationship to the digital pulse train generated by the crankshaft trigger wheel. The measured phase difference between the camshaft and crankshaft pulse trains is directly related to the camshaft phase. This article describes how to measure and control the cam phase using the Drivven Low-Side Driver Module Kit and the Drivven Engine Position Tracking (EPT) VI for the NI LabVIEW FPGA and LabVIEW Real-Time modules. You can implement the example code provided on a PXI or CompactRIO hardware platform from NI.

Measuring Cam Phase

Assume that you have a single cam phaser to be controlled for a 4‐stroke engine. Such a system contains a production crank trigger wheel and a production cam trigger wheel. Also assume a typical N‐M crank trigger pattern and a multipulse, multiwidth cam trigger pattern. For example, the Delphi cam phaser trigger wheel typically emits about 4 pulses per cam rotation, and each pulse has a different width. Use a Drivven EPT N‐M VI (see Drivven EPT documentation) to track the angular position of the crankshaft over a 4‐stroke cycle (720 degrees). The Drivven EPT N‐M VI requires the cam signal to be high during every other crankshaft tooth gap. If this is not realized by default, Drivven provides FPGA‐based Boolean signal manipulation VIs that offset the incoming position of the cam pulses in terms of a specified number of crank pulses. Then you can extend the offset cam signal to provide sufficient cover over the crank gap. You must study the raw crank and cam signals to determine how much cam offset and extension you need to satisfy the EPT VI requirements. In addition, you need to account for the total range of cam phaser motion. You also may implement filter and inversion logic.

Once you have the EPT tracking crank position (SyncStopped = FALSE), then you can capture the crank position of one of the rising or falling edges of the raw cam signal. Drivven provides an FPGA VI called angle_capture_vt_reva.vi for this purpose. The cam signal may have multiple rising and falling edges. If so, then you can generate an angle‐based window with the FPGA VI called aap_vt_reva.vi to mask all but one particular edge over an angular window. You can convert the resulting captured absolute crank angle ticks (CATs) of the cam rising edge to crank angle degrees (CADs) with respect to a particular cylinder top dead center (TDC) angle in the real-time application. This is the measured cam phase as shown in Figure 1.

Figure 1. This image depicts how you determine the cam phase.
 

Controlling the Cam Phaser

You control the cam phaser oil control valve solenoid using a PWM output from a low-side driver channel from either the Drivven Low-Side Driver Module Kit or the Drivven PFI Driver Module Kit. In the example code provided, the Low-Side Driver Module Kit is used. The real-time application should use the measured cam phase along with a PID control VI from Drivven or NI to generate a duty-cycle output for controlling the cam phase to a desired setpoint. You can sent the resulting PWM duty cycle to the desired low-side driver channel along with the desired PWM frequency.
 

Controller Implementation Project

The cam phase controller example project includes a real-time PXI target, which features an NI PXI‐7813R digital RIO FPGA target. You connect an NI 9151 R Series expansion chassis to the PXI FPGA module and use the Drivven Low-Side Driver Module Kit and an NI 9411 C Series digital input module. Top-level VIs fall under their respective targets. The FPGA VI is responsible for tracking the engine position and measuring the cam position. The FPGA VI also interfaces with the Drivven Low-Side Driver Module Kit and NI 9411 module. The RT VI is responsible for converting the measured cam phase to engineering units, executing the control algorithms, and converting the low-side driver

PWM output to values that the FPGA can use. The LabVIEW Project Explorer is shown in Figure 2.

Figure 2. Cam Phaser Control LabVIEW Project Explorer
 

FPGA Implementation

The FPGA block diagram is described in Figure 3.

Figure 3. Cam Phaser Control—FPGA
 

1. You should place all of the required FPGA code in a single-cycle loop. This requires the entire loop to execute at the FPGA clock rate (typically 40 MHz).
2. The EPT N‐M VI reads the cam and crank pattern to determine the current crank angle at any time. The raw crank and cam signals enter the FPGA from an NI 9411 module for this example. The Drivven AD Combo Module Kit is required if the position sensors are VR type sensors. Using the Drivven Integrating Filter VI for glitch filtering is recommended. You may need the Signal Offset and Signal Extension VIs to manipulate the cam signal to meet EPT requirements.
3. Use the filtered cam signal for the angle capture. This code shows only one phaser, but you may use multiple cam phasers.
4. An angle‐based window is generated by the Angle‐Angle‐Pulse VI configured by the StartPosition and EndPosition parameters.
5. During the window, the crank position of the cam rising edge is captured to the CurrentPosition output of the angle capture VI.
6. The low-side driver creates a PWM current drive to control the phaser oil control valve. The parameters of the low-side driver are set in the real-time application.

 

Real-Time Implementation

The real-time block diagram is shown in Figure 4.

Figure 4. Cam Phaser Control—RT
 

1. Start the specified FPGA VI and create a reference.
2. Use a 5 or 10 ms loop for engine control. Apply a Timed Loop so you can adjust its priority with respect to other loops.
3. Calculate the EPT control parameters and combine them in a cluster (refer to the EPT User Manual).
4. Calculate the maximum CAT value (refer to the EPT User Manual).
5. Write the various crank/cam signal filtering and manipulation parameters along with the EPT control cluster. Read the EPT data cluster.
6. Display the EPT data.
7. Convert the window StartPosition and EndPosition, which are in CADs, to CATs for FPGA implementation.
8. Write the window parameters to the FPGA and read the cam phaser position.
9. Convert the cam phaser current position from CATs to CADs.
10. Convert the cam phaser position to an offset angle with respect to a fixed crank angle.
11. Use a PID Controller VI to control the PWM duty cycle. You can further condition the PID Controller VI output by using a feedforward parameter and additional limits (not shown here).
12. Convert the duty cycle and frequency to period and pulse width values that the FPGA can use (refer to the Low-Side Driver Module Kit User Manual).
13. Combine the low-side control values into the control cluster.
14. Transfer the low-side control cluster to the FPGA.

 

Conclusion

While sophisticated electrically controlled engine subsystems promise increased efficiency and low emissions for internal combustion engines, controlling them all with a single platform can be difficult to manage. The engine control product line by NI and Drivven offers the tools you need to get your engines up and running.

For more information or a free consultation on your engine control application, contact Drivven at (210) 248-9308 or info@drivven.com.