Assume that you have a single cam phaser to be controlled for a 4‐stroke engine. Such a system contains a production crank trigger wheel and a production cam trigger wheel. Also assume a typical N‐M crank trigger pattern and a multipulse, multiwidth cam trigger pattern. For example, the Delphi cam phaser trigger wheel typically emits about 4 pulses per cam rotation, and each pulse has a different width. Use a Drivven EPT N‐M VI (see Drivven EPT documentation) to track the angular position of the crankshaft over a 4‐stroke cycle (720 degrees). The Drivven EPT N‐M VI requires the cam signal to be high during every other crankshaft tooth gap. If this is not realized by default, Drivven provides FPGA‐based Boolean signal manipulation VIs that offset the incoming position of the cam pulses in terms of a specified number of crank pulses. Then you can extend the offset cam signal to provide sufficient cover over the crank gap. You must study the raw crank and cam signals to determine how much cam offset and extension you need to satisfy the EPT VI requirements. In addition, you need to account for the total range of cam phaser motion. You also may implement filter and inversion logic.Once you have the EPT tracking crank position (SyncStopped = FALSE), then you can capture the crank position of one of the rising or falling edges of the raw cam signal. Drivven provides an FPGA VI called angle_capture_vt_reva.vi for this purpose. The cam signal may have multiple rising and falling edges. If so, then you can generate an angle‐based window with the FPGA VI called aap_vt_reva.vi to mask all but one particular edge over an angular window. You can convert the resulting captured absolute crank angle ticks (CATs) of the cam rising edge to crank angle degrees (CADs) with respect to a particular cylinder top dead center (TDC) angle in the real-time application. This is the measured cam phase as shown in Figure 1.Figure 1. This image depicts how you determine the cam phase.
You control the cam phaser oil control valve solenoid using a PWM output from a low-side driver channel from either the Drivven Low-Side Driver Module Kit or the Drivven PFI Driver Module Kit. In the example code provided, the Low-Side Driver Module Kit is used. The real-time application should use the measured cam phase along with a PID control VI from Drivven or NI to generate a duty-cycle output for controlling the cam phase to a desired setpoint. You can sent the resulting PWM duty cycle to the desired low-side driver channel along with the desired PWM frequency.
The cam phase controller example project includes a real-time PXI target, which features an NI PXI‐7813R digital RIO FPGA target. You connect an NI 9151 R Series expansion chassis to the PXI FPGA module and use the Drivven Low-Side Driver Module Kit and an NI 9411 C Series digital input module. Top-level VIs fall under their respective targets. The FPGA VI is responsible for tracking the engine position and measuring the cam position. The FPGA VI also interfaces with the Drivven Low-Side Driver Module Kit and NI 9411 module. The RT VI is responsible for converting the measured cam phase to engineering units, executing the control algorithms, and converting the low-side driverPWM output to values that the FPGA can use. The LabVIEW Project Explorer is shown in Figure 2.Figure 2. Cam Phaser Control LabVIEW Project Explorer
The FPGA block diagram is described in Figure 3.Figure 3. Cam Phaser Control—FPGA
The real-time block diagram is shown in Figure 4.Figure 4. Cam Phaser Control—RT
While sophisticated electrically controlled engine subsystems promise increased efficiency and low emissions for internal combustion engines, controlling them all with a single platform can be difficult to manage. The engine control product line by NI and Drivven offers the tools you need to get your engines up and running.For more information or a free consultation on your engine control application, contact Drivven at (210) 248-9308 or firstname.lastname@example.org.
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