Figure 1 Download and Install Order
1. Download and install LabVIEW 2015
2. Download and install LabVIEW FPGA Module 2015
3. Download and install LabVIEW 2015 FPGA Module Xilinx Tools Vivado 2014.4
4. Download and install the DSDB Driver
5. Install Digilent Drivers
- Navigate to: C:\NIFPGA\programs\Vivado2014_4\data\xicom\cable_drivers\nt64\digilent
- Double click: install_digilent.exe to install the Digilent drivers.
6. Restart the computer.
Starting a Project in LabVIEW
Creating a Project
- Launch LabVIEW.
- In the Getting Started window, click Empty Project. The new project opens in the Project Explorer window.
- Save the project as FPGA_Design.lvproj.
Creating an FPGA Target VI
1. In the Project Explorer window, right-click My Computer and select New»Targets and Devices.
2. In the Add Targets and Devices on My Computer window, select New target or device, expand Digilent, and highlight Digital Systems Development Board. Click OK. The target is discovered and the target and target properties are loaded into the project tree.
3. In the Project Explorer window, right-click FPGA Target (DSDB, Digital Systems Development Board), and select New»VI. A blank VI opens. Select the block diagram window.
4. In the Project Explorer window FPGA Target (DSDB, Digital Systems Development Board) tree view, select SW0 and LED1 and drag them onto the block diagram as shown in the image below.
5. In the LabVIEW block diagram, wire SW0 output to the LED1 input.
6. In the Project Explorer window FPGA Target (DSDB, Digital Systems Development Board) tree view, select BTN0 and LED2 and drag them onto the block diagram.
7. In the LabVIEW block diagram, wire BTN0 output to the LED2 input.
8. Add a While Loop around the resources.
9. Wire a false constant to the stop condition of the While Loop as shown below.
10. Save the VI as FPGA_Design.vi.
Running the FPGA VI
1. Verify that the USB cable is connected to the DSDB and host PC, and the power switch is moved to the ON position.
2. Open the front panel of FPGA_Design.vi.
3. Click the Run button to run the VI.
4. The application compiles VHDL code and generates a bitstream file that is downloaded into the FPGA configuration storage. The Generating Intermediate Files window opens and displays the compilation progress. The LabVIEW FPGA Compile Server window opens and runs. Choose compile locally. The compilation takes several minutes. See an image of the compile server window below.
5. When the compilation finishes, click the Stop Server button to close the LabVIEW FPGA Compile Server.
6. Click Close in the Successful Compile Report window as shown in the image below.
The application is running on the FPGA board at this time.
7. Move switch SW0 up and down; LED1 should correspondingly light and turn off.
8, Press button BTN0; LED2 should correspondingly light and turn off.