FPGA Loop Timer Express VI Initial Delay

Updated May 23, 2023

Reported In


  • LabVIEW FPGA Module

Issue Details

I am outputting a square wave using a Loop Timer configured to use milliseconds (mSec) to control the period. It is set to wait for 4 ms on each loop iteration. For some reason it takes 1 ms for the first output to appear. However, when I configure the Loop Timer to use microseconds (uSec), and tell it to wait 4000 µs, the delay of 1 ms is not there. Why?


On the first iteration, the Loop Timer Express VI waits to synchronize its execution with the edge of the appropriate (ms, µs or ticks) counter. This causes an initial delay on the lower resolution instances (mSec and uSec) of up to 1 ms and 1 µs respectively.


Additional Information

Assume the following FPGA VI:

In this code, three square waveforms are generated and read in parallel:
  1. Firstly, the outputs are re-set to 0.
  2. Then three data generation loops start executing, all beginning with an Loop Timer Express VI. The first one is using the mSec setting, the second one the uSec setting, and the last one is using the Ticks counter.
  3. After each Loop Timer has returned, each respective output is set to 1.
  4. On the next loop iteration, the counters wait for the defined period(s) of time, afterwards -1 is written to the outputs.
  5. This repeats.
  6. In parallel, all outputs are read at a high rate right from the beginning. The values read are transferred to a PC using a FIFO.

The following chart is created from the values read from the FIFO:

It can be recognized that all three outputs have a delay before switching from the initial 0 to ±1. These initial delays vary:
  • For the loop using the Loop Timer Express VI set to use Ticks (green line with circles) it is just one sample. This is because the acquisition loop starts roughly at the same time as the generation loop.
  • The Loop Timer Express VI set to use uSec (plain red line) has a delay of up to one microsecond. That's the maximum duration the timer needs to wait for an edge of the clock signal.
  • For the loop using the Loop Timer Express VI set to use mSec (white marked line with x's), the first transition to +1 is out of scope of this diagram. It happens after 1 ms maximum, however the diagram's x range covers only about 0.06 ms.