Why Do My Parallel SubVIs Execute in Series Within Timed Loop?

Updated Apr 14, 2020

Reported In

Software

  • LabVIEW
  • LabVIEW Real-Time Module

Issue Details

I have put two same subVIs inside a timed loop in LabVIEW program, I noticed when I arranged both of my SubVIs in parallel within a timed loop, it takes same amount of time as I arranged it in series. But if I run same code within while loop, it takes as much time as expected when I run them in either series or parallel.

Why is this occurred and how to perform parallel execution?

   
  

Solution

When code that is contained in a Timed Loop is run on a dual-core or multicore system, a single unique thread will be created. All the code within the Timed Loop will share on the same unique thread. If the code consists of multiple loops running as fast as possible, LabVIEW will not be able to switch to other task using the single thread which will looks as if the code is running in series even through being configured in parallel arrangement. To enable parallel execution, it is better to use While Loop instead as it switches between available threads instead of making use of just one unique thread.

Additional Information

The timed loop acts as a while loop but has special characteristics that can help you optimize performance based on the multicore hardware configuration.  In particular, it's a useful characteristic on real-time systems and where optimizing for cache is important. In addition to executing in a single thread, the loop can set processor affinity, which is a mechanism to assign that thread to a particular CPU (and hence help optimize for cache).

It's important to note that parallel patterns that work well within a regular while loop (such as data parallelism and pipelining), will not work with a timed loop, because no parallelism can be achievable in a single thread.  Instead, the techniques can be implemented using multiple timed loops, for example, with pipelining one timed loop can represent a unique stage in the pipeline, with data transfer between loops via FIFOs.