Missing Data with DMA FIFO

Solution

Missing data from a DMA FIFO is usually due to improper DMA architecture. The points below are several common issues related to missing data that developers run into when using a DMA FIFO.

The acquisition code of the FPGA has sections of code that take an undefined amount of time. If data should be acquired at a given loop rate and the FPGA is waiting on the host for a value change or an interrupt, the FPGA will stop acquiring and data will be lost.
Data is being read from the FIFO out of order. This can occur when interleaving data into the FIFO and you do not specify to read an integer multiple of the number of channels.
The DMA FIFO is overflowing. The KnowledgeBase article Missing Data When Using DMA FIFO With High Sample Rates on FPGA goes into more detail on this subject. However, there are several methods for avoiding overflows given below.
- Monitor if the Write (FIFO Method) times out. If timeout is true on the Write function, this is a sign that your buffer is not set appropriately.
- Read data in large amounts on the host. This helps limit the computational overhead of data communication for the host.
- Read data from the FIFO with a standard architecture. Follow the guide for Designing a Host VI to Read Data in DMA Application.

Missing Data with DMA FIFO

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