Solution
This is expected behavior. If you use certain FPGA resources and you execute the FPGA VI in simulation mode using simulated I/O, the resource uses simulated time instead of real time. Simulated time might be faster than real time depending on the number of events that occur during the simulation.
The following resources use simulated time on the host:
- While Loops
- Single-Cycle Timed Loops
- Wait (Simulated Time) VI
- Loop Timer Express VI
- Tick Count Express VI
- FIFOs, except DMA FIFOs
- Wait on Occurrence with Timeout in Ticks Function
- Interrupt VI, when Wait Until Cleared is TRUE