FPGA Timing Not Working Correctly in Simulation Mode

Updated Nov 21, 2019

Reported In


  • LabVIEW FPGA Module

Issue Details

When using timing functions in LabVIEW FPGA in Simulation Mode, I believe I am observing unexpected behavior. How can I fix this?


This is expected behavior. If you use certain FPGA resources and you execute the FPGA VI in simulation mode using simulated I/O, the resource uses simulated time instead of real time. Simulated time might be faster than real time depending on the number of events that occur during the simulation.

The following resources use simulated time on the host:

  • While Loops
  • Single-Cycle Timed Loops
  • Wait (Simulated Time) VI
  • Loop Timer Express VI
  • Tick Count Express VI
  • FIFOs, except DMA FIFOs
  • Wait on Occurrence with Timeout in Ticks Function
  • Interrupt VI, when Wait Until Cleared is TRUE

Additional Information

Compiling an FPGA VI can take minutes to hours. However, you can test the logic of an FPGA VI before compiling it by executing the FPGA VI in simulation mode using simulated I/O. When you use this test method, LabVIEW generates random data for the inputs or uses a custom VI that you create to provide I/O. You also can use the FPGA Desktop Execution Node to communicate with FPGA resources that you select and to debug your FPGA design.