Loop Timer Express VI Is Not Working Correctly in FPGA Simulated I/O Mode

Updated Apr 4, 2019

Reported In


  • NI-9149


  • LabVIEW 2018
  • LabVIEW 2018 FPGA Module

Issue Details

I want to test my code on LabVIEW before FPGA compilation, but when I set the execution mode to Simulated I/O, LED indicator blinks faster than the value set in Loop Timer .


If you use node that takes up FPGA resources and you execute the FPGA VI in simulation mode using simulated I/O, the resource uses simulated time instead of real time. Simulated time might be faster than real time depending on the number of events that occur during the simulation.

The following resources use simulated time on the development computer:

  • While Loops
  • Single-Cycle Timed Loops
  • Wait (Simulated Time) VI
  • Loop Timer Express VI
  • Tick Count Express VI
  • FIFOs, except DMA FIFOs
  • Wait on Occurrence with Timeout in Ticks Function
  • Interrupt VI, when Wait Until Cleared is TRUE

Additional Information

Starting from LabVIEW FPGA 2013, some FPGA resources now use simulated time rather than real time when you execute the VI on a development computer with simulated I/O.