Timing SCTL Loop with External Clock

Updated May 22, 2023

Reported In


  • NI-6583
  • PXIe-7976


  • LabVIEW FPGA Module

Issue Details

I am using FAM NI 6583 together with NI PXIe-7976 . In my application, I am wiring directly DDC_A_Strobe to the loop as a timing signal source (133MHz), basing on NI 6583 Channel CLIP configuration. When I start the target application, I receive the following error: 

An error was detected in the communication between the host computer and the FPGA target. 

If you are using any external clocks, make sure they are connected and within the supported specifications. Also verify that the rate of any external clocks match the specified clock rates. If you are generating your clocks internally, please contact National Instruments Technical Support.

I prepared other application just for measuring the frequency of the signal with given constant timing (310MHz). The test was successful, so it is not the fault of the clock itself.


The Host code is trying to access some logic on the FPGA connected to this external clock before everything is ready. Either FAM initialization hasn't finished yet or the external clock signal isn't actually running yet. The solution is to ensure you aren't trying to read FPGA logic clocked by this external signal when that signal isn't present. If it's known that the clock signal is continuous, then the easy solution is to put something in the Host code that will keep it from trying to access the FPGA logic before the clock is ready. The same actions are done in the example NI 6583 Continuous Acquisition DDR - External Clock.lvproj.  You can access it at Help»Find Examples, then select Hardware Input and Output»FlexRIO»IO Modules.