Design Rule Error: Net "XX" Is Connected to Net "YY" in Ultiboard

Updated Jan 4, 2019

Reported In


  • Ultiboard Full
  • Multisim

Issue Details

In the DRC Tab in Ultiboard I am getting (Design rule error: Net "XX" is connect to net "YY"), where XX and YY are two different nets I have in my design.


Why am I getting this error and how can I avoid it?


Please note that this a warning not an error you can see the difference in the DRC Tab in the Ultiboard help. The warning is produced because you have two nets connected together in the design, these nets weren't connected in your Multisim circuit. This can happen if one of your parts footprint is inherently connecting two nets together. You can ignore the warning if you are sure that this is an expected behaviour or modify the circuit in Multisim to have both nets connected together (single net).