FPGA Bitfile Won't Run Error -61207 Diagramreset Did Not Clear Within the Timeout Period

Updated Jan 8, 2019

Issue Details

When attempting to compile and run a simple FPGA VI containing only a while loop and an indicator to show the number of iterations, an error message shows :
"FPGA bitfile won't run error -61207 DiagramReset did not clear within the timeout period."



This issue can be caused due to a faulty power supply, and can occur if the MXI cRIO is rebooted or loses power while the host computer remains powered and running. This issue can be resolved by following these steps:
  1. Power off the host computer
  2. Power off the cRIO-9157
  3. Power on the cRIO-9157
  4. Power on the host computer
Another step to try to solve this would be to test the power supply on another known working chassis and if this causes issues to then replace the power supply altogether.

In a previous case, the lights on the chassis were all powered up and it seemed as though the chassis was fully functioning and working well although, when the power supply was replaced the error no longer occurred and the system ran smoothly.


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