Unlock Error Occurs When Using Ref Clock of PXIe Chassis in Other Equipment

Updated Dec 17, 2018

Reported In


  • PXIe-1082
  • PXI-1042
  • PXI-1042Q
  • PXI-1044
  • PXI-1045
  • PXIe-1062Q
  • PXIe-1065
  • PXIe-1066DC
  • PXIe-1075
  • PXIe-1082DC
  • PXIe-1085
  • PXIe-1086
  • PXIe-1095

Issue Details

I want to use a 10 MHz reference Clock on the backplane of the PXIe-1082 Chassis to use as a clock source for a third-party device. However, an unlock error occurs on third-party equipment. What causes this?


The reference clock on the chassis backplane of PXIe-1082 is not the signal that passed the phase locked loop. Therefore, this signal may not be recognized as a locked signal by other equipment. Therefore, it is recommended to use other signals passed PLL as a clock source in order to synchronize with other equipment. Generally, the clock signal generated by module pass PLL.

Additional Information

A Phase-Locked Loop(PLL) is a feedback circuit designed to allow one circuit board to synchronize the phase of its onboard clock with an external timing signal. The circuit then adjusts the phase of the oscillator's clock signal to match the phase of the reference signal. Thus, the original reference signal and the new signal are precisely in phase with each other. The basic components of a Phase-Locked Loop(PLL) are a stable reference oscillator, a phase detector, a frequency divider, a voltage-controlled oscillator(VCO), amplifiers, and filters. The following figure shows a simplified PLL block diagram. 

You can learn more detailed concepts through the pii.vi link below.


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