Connecting Guard Pins on My PXIe 4162

Updated Feb 20, 2019

Reported In


  • PXIe-4162

Issue Details

I am starting to use the PXIe 4162 and I would like to start using the benefits of the guarding that is available for this card. However, I am not being able to find how to connect this guard pins to my DUT.


The main idea of guarding is to remove the effects of leakage currents and parasitic capacitances between HI and LO. To understand more details of guarding you can refer to this document.

If your DUT is directly connected to the PXIe 4162 cable then there is no additional connection needed for the guard pins, since the cable already takes care of the guard. However, if you are using a PCB to interface with your DUT, then you may also consider to implement the bridge for this guarded line, to avoid potential leakages on this other board.


Additional Information

Guarding minimize parasitic capacitances of cabling for your system. Guard sources current less than 10 nA range, charges stray capacitance in cable and PCB ~10.000x faster, hence HI sees virtually no capacitance due to VHI ~= VGuard

The screenshot below details how a regular coaxial cable could lead to leakage currents between HI and LO

After implementing guarding and using triaxial cables we would reduce that leakage current to ~0

To see this in a circuit, you can refer to this diagram below where we see how the leakage currents will remain on the guarding node, giving us a more accurate signal in the SMU output


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