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Synchronizing the NI 5783 I/O Clock with the FPGA Clock

Updated Nov 6, 2018

Reported In


  • NI-5783
  • PXI FPGA Module for FlexRIO


  • LabVIEW FPGA Module

Issue Details

I'm capturing data in one loop that's running off of the I/O clock and I'm trying to pass that data to a different loop that runs off of the FPGA clock. I'm using a buffer to pass data between these loops but I keep seeing a buffer overflow error. The two loops are supposed to be running at the same rate, but I don't think they're synchronized. Is there a way to synchronize the I/O clock with the FPGA clock?


It is possible to synchronize the I/O clock of the NI 5783 with the FPGA clock by changing the clock source of the I/O clock. In the help documentation for the NI 5783 CLIP, there's a list of user commands. The first command is the ability to configure clocks. One of the Command Arguments, Arg 0, allows you to choose the clock source for the I/O clock. 

By default, the argument is set to "0" which means the clock source is the internal VCXO clock. If you change that setting to "2", the clocking source will be changed to the "Back Plane Ref" clock. This setting synchronizes the I/O clock with the backplane clock. In addition, the FPGA clocks are already synchronized to the backplane clock by default. Since both the FPGA clock and the I/O clock are synchronized to the same source, they are now synchronized with each other. 

Additional Information

The steps mentioned above apply specifically to the NI 5783. Not every FlexRIO Adapter Module(FAM) will have those same exact settings. If you are not using the NI 5783, please check the CLIP help file for your specific FAM. 


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