Solution
There are two major clocks used in USRP RIO: FPGA clock and ADC/DAC clock. The two clocks operate independently but all are derived from the same oscillator, so the clock signals are synchronized by default.
The clock for driving the FPGA is 40 MHz as the default clock, and you can use this clock to derive the clock with different frequency. On the other hand, the clock for driving the ADC/DAC depends on the type of USRP, and the frequency value is fixed at its maximum value.
For NI USRP RIO products, It is usually set at 120MHz or 200MHz and you can not change this value. This clock is indicated as Data Clock in the top-level FPGA VI. This clock rate is different from the IQ signal streaming rate (IQ rate) that users can change at the host side. The IQ rate is interpolated/decimated via DSP in the FPGA and is then compatible with the ADC/DAC sampling rate. If an external 10 MHz reference signal is received rather than an internal reference signal as the source of the clock signal, the oscillator will be phase-locked (PLL) with this reference signal. Therefore, you can synchronize multiple USRPs using the REF IN/OUT on the rear of USRP.